)]}'
{
  "commit": "1ac489c8e38ecaeccba7d8826273395eaba2db6c",
  "tree": "82defe12fa67519fb307f5a727d84eb06a2c6d60",
  "parents": [
    "b9d6cbd4dc1def3f15b7d5ebb8cb4714bdad22bf"
  ],
  "author": {
    "name": "Philip Reames",
    "email": "preames@rivosinc.com",
    "time": "Wed May 07 08:15:44 2025 -0700"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Wed May 07 08:15:44 2025 -0700"
  },
  "message": "[RISCV] Initial codegen support for zvqdotq extension (#137039)\n\nThis patch adds pattern matching for the basic usages of the dot product\ninstructions introduced by the experimental zvqdotq extension. It\nspecifically only handles the case where the pattern is feeding a i32\nsum reduction as we need to reassociate the reduction tree to use these\ninstructions.\n\nThe vecreduce_add (sext) and vecreduce_add (zext) cases are included\nmostly to exercise the VX matchers. For the generic matching, we fail to\nmatch due to an order of combine issue which results in the bitcast\nbeing separated from the splat.\n\nI chose to do this lowering as an early combine so as to avoid having to\nintegrate the entire logic into the reduction lowering flow. In\nparticular, that would get a lot more complicated as we extend this to\nhandle add-trees feeding the reductions.",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "86f8873c135ef865560e0f5623829b8311501c02",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/RISCV/RISCVISelLowering.cpp",
      "new_id": "698b951ad492873d5998fa79310c7afc7a0c7fb0",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/RISCV/RISCVISelLowering.cpp"
    },
    {
      "type": "modify",
      "old_id": "ba24a0c324f51df649e437f17479c8f0af1e8d1c",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/RISCV/RISCVISelLowering.h",
      "new_id": "3f1fce5d9f7e504debb5f25e745349fc57822186",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/RISCV/RISCVISelLowering.h"
    },
    {
      "type": "modify",
      "old_id": "205fffd5115ee412d3fac79c04bf271c703d18d1",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/RISCV/RISCVInstrInfoZvqdotq.td",
      "new_id": "6018958f6eb274b2158ad3a06ad2af1b247e7fb6",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/RISCV/RISCVInstrInfoZvqdotq.td"
    },
    {
      "type": "modify",
      "old_id": "25192ea19aab3650c153039eba4d0bf34c56257d",
      "old_mode": 33188,
      "old_path": "llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvqdotq.ll",
      "new_id": "e48bc9cdfea4eb329f5baa1e1142294c880d73a1",
      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvqdotq.ll"
    }
  ]
}