[RISCV] Add tests for fixed-length vwadd[u].{w,v}v with disjoint or. NFC
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
index 9997646..5e7d1b9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
@@ -876,3 +876,107 @@
%e = add <2 x i64> %c, %d
ret <2 x i64> %e
}
+
+; %x.i32 and %y.i32 are disjoint, so DAGCombiner will combine it into an or.
+define <4 x i32> @vwaddu_vv_disjoint_or_add(<4 x i8> %x.i8, <4 x i8> %y.i8) {
+; CHECK-LABEL: vwaddu_vv_disjoint_or_add:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vzext.vf2 v10, v8
+; CHECK-NEXT: vsll.vi v8, v10, 8
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vzext.vf2 v10, v8
+; CHECK-NEXT: vzext.vf4 v8, v9
+; CHECK-NEXT: vor.vv v8, v10, v8
+; CHECK-NEXT: ret
+ %x.i16 = zext <4 x i8> %x.i8 to <4 x i16>
+ %x.shl = shl <4 x i16> %x.i16, splat (i16 8)
+ %x.i32 = zext <4 x i16> %x.shl to <4 x i32>
+ %y.i32 = zext <4 x i8> %y.i8 to <4 x i32>
+ %add = add <4 x i32> %x.i32, %y.i32
+ ret <4 x i32> %add
+}
+
+define <4 x i32> @vwaddu_vv_disjoint_or(<4 x i16> %x.i16, <4 x i16> %y.i16) {
+; CHECK-LABEL: vwaddu_vv_disjoint_or:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vor.vv v9, v8, v9
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vzext.vf2 v8, v9
+; CHECK-NEXT: ret
+ %x.i32 = zext <4 x i16> %x.i16 to <4 x i32>
+ %y.i32 = zext <4 x i16> %y.i16 to <4 x i32>
+ %or = or disjoint <4 x i32> %x.i32, %y.i32
+ ret <4 x i32> %or
+}
+
+define <4 x i32> @vwadd_vv_disjoint_or(<4 x i16> %x.i16, <4 x i16> %y.i16) {
+; CHECK-LABEL: vwadd_vv_disjoint_or:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vor.vv v9, v8, v9
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsext.vf2 v8, v9
+; CHECK-NEXT: ret
+ %x.i32 = sext <4 x i16> %x.i16 to <4 x i32>
+ %y.i32 = sext <4 x i16> %y.i16 to <4 x i32>
+ %or = or disjoint <4 x i32> %x.i32, %y.i32
+ ret <4 x i32> %or
+}
+
+define <4 x i32> @vwaddu_vx_disjoint_or(<4 x i16> %x.i16, i16 %y.i16) {
+; CHECK-LABEL: vwaddu_vx_disjoint_or:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vor.vx v9, v8, a0
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vzext.vf2 v8, v9
+; CHECK-NEXT: ret
+ %x.i32 = zext <4 x i16> %x.i16 to <4 x i32>
+ %y.head = insertelement <4 x i16> poison, i16 %y.i16, i32 0
+ %y.splat = shufflevector <4 x i16> %y.head, <4 x i16> poison, <4 x i32> zeroinitializer
+ %y.i32 = zext <4 x i16> %y.splat to <4 x i32>
+ %or = or disjoint <4 x i32> %x.i32, %y.i32
+ ret <4 x i32> %or
+}
+
+define <4 x i32> @vwadd_vx_disjoint_or(<4 x i16> %x.i16, i16 %y.i16) {
+; CHECK-LABEL: vwadd_vx_disjoint_or:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vor.vx v9, v8, a0
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsext.vf2 v8, v9
+; CHECK-NEXT: ret
+ %x.i32 = sext <4 x i16> %x.i16 to <4 x i32>
+ %y.head = insertelement <4 x i16> poison, i16 %y.i16, i32 0
+ %y.splat = shufflevector <4 x i16> %y.head, <4 x i16> poison, <4 x i32> zeroinitializer
+ %y.i32 = sext <4 x i16> %y.splat to <4 x i32>
+ %or = or disjoint <4 x i32> %x.i32, %y.i32
+ ret <4 x i32> %or
+}
+
+define <4 x i32> @vwaddu_wv_disjoint_or(<4 x i32> %x.i32, <4 x i16> %y.i16) {
+; CHECK-LABEL: vwaddu_wv_disjoint_or:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vzext.vf2 v10, v9
+; CHECK-NEXT: vor.vv v8, v8, v10
+; CHECK-NEXT: ret
+ %y.i32 = zext <4 x i16> %y.i16 to <4 x i32>
+ %or = or disjoint <4 x i32> %x.i32, %y.i32
+ ret <4 x i32> %or
+}
+
+define <4 x i32> @vwadd_wv_disjoint_or(<4 x i32> %x.i32, <4 x i16> %y.i16) {
+; CHECK-LABEL: vwadd_wv_disjoint_or:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vsext.vf2 v10, v9
+; CHECK-NEXT: vor.vv v8, v8, v10
+; CHECK-NEXT: ret
+ %y.i32 = sext <4 x i16> %y.i16 to <4 x i32>
+ %or = or disjoint <4 x i32> %x.i32, %y.i32
+ ret <4 x i32> %or
+}
