llvm/test/CodeGen/AArch64/redundant-mov-from-zero-extend.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O3 -mtriple=aarch64-linux-gnu < %s | FileCheck %s

define i32 @test(i32 %input, i32 %n, i32 %a) {
; CHECK-LABEL: test:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    cbz w1, .LBB0_2
; CHECK-NEXT:  // %bb.1:
; CHECK-NEXT:    mov w0, wzr
; CHECK-NEXT:    ret
; CHECK-NEXT:  .LBB0_2: // %bb.0
; CHECK-NEXT:    add w8, w0, w1
; CHECK-NEXT:    mov w0, #100
; CHECK-NEXT:    cmp w8, #4
; CHECK-NEXT:    b.hi .LBB0_5
; CHECK-NEXT:  // %bb.3: // %bb.0
; CHECK-NEXT:    adrp x9, .LJTI0_0
; CHECK-NEXT:    add x9, x9, :lo12:.LJTI0_0
; CHECK-NEXT:    adr x10, .LBB0_4
; CHECK-NEXT:    ldrb w11, [x9, x8]
; CHECK-NEXT:    add x10, x10, x11, lsl #2
; CHECK-NEXT:    br x10
; CHECK-NEXT:  .LBB0_4: // %sw.bb
; CHECK-NEXT:    add w0, w2, #1
; CHECK-NEXT:    ret
; CHECK-NEXT:  .LBB0_5: // %bb.0
; CHECK-NEXT:    cmp w8, #200
; CHECK-NEXT:    b.ne .LBB0_10
; CHECK-NEXT:  // %bb.6: // %sw.bb7
; CHECK-NEXT:    add w0, w2, #7
; CHECK-NEXT:    ret
; CHECK-NEXT:  .LBB0_7: // %sw.bb1
; CHECK-NEXT:    add w0, w2, #3
; CHECK-NEXT:    ret
; CHECK-NEXT:  .LBB0_8: // %sw.bb3
; CHECK-NEXT:    add w0, w2, #4
; CHECK-NEXT:    ret
; CHECK-NEXT:  .LBB0_9: // %sw.bb5
; CHECK-NEXT:    add w0, w2, #5
; CHECK-NEXT:  .LBB0_10: // %return
; CHECK-NEXT:    ret
entry:
  %b = add nsw i32 %input, %n
  %cmp = icmp eq i32 %n, 0
  br i1 %cmp, label %bb.0, label %return

bb.0:
  switch i32 %b, label %return [
    i32 0, label %sw.bb
    i32 1, label %sw.bb1
    i32 2, label %sw.bb3
    i32 4, label %sw.bb5
    i32 200, label %sw.bb7
  ]

sw.bb:
  %add = add nsw i32 %a, 1
  br label %return

sw.bb1:
  %add2 = add nsw i32 %a, 3
  br label %return

sw.bb3:
  %add4 = add nsw i32 %a, 4
  br label %return

sw.bb5:
  %add6 = add nsw i32 %a, 5
  br label %return

sw.bb7:
  %add8 = add nsw i32 %a, 7
  br label %return

return:
  %retval.0 = phi i32 [ %add8, %sw.bb7 ], [ %add6, %sw.bb5 ], [ %add4, %sw.bb3 ], [ %add2, %sw.bb1 ], [ %add, %sw.bb ], [ 100, %bb.0 ], [ 0, %entry ]
  ret i32 %retval.0
}