llvm/test/CodeGen/AArch64/neon-dotpattern.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple aarch64-none-linux-gnu -mattr=+dotprod    < %s | FileCheck %s

define fastcc void @test_sdot_v4i8(i8* noalias nocapture %0, i8* noalias nocapture readonly %1, i8* noalias nocapture readonly %2) {
; CHECK-LABEL: test_sdot_v4i8:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ldr w8, [x2]
; CHECK-NEXT:    dup v0.2s, wzr
; CHECK-NEXT:    ldr w9, [x1]
; CHECK-NEXT:    fmov s1, w8
; CHECK-NEXT:    fmov s2, w9
; CHECK-NEXT:    sdot v0.2s, v1.8b, v2.8b
; CHECK-NEXT:    fmov x8, d0
; CHECK-NEXT:    str w8, [x0]
; CHECK-NEXT:    ret
entry:
  %3 = bitcast i8* %0 to i32*
  %4 = load i8, i8* %1, align 1
  %5 = sext i8 %4 to i32
  %6 = load i8, i8* %2, align 1
  %7 = sext i8 %6 to i32
  %8 = mul nsw i32 %7, %5
  %9 = getelementptr inbounds i8, i8* %1, i64 1
  %10 = load i8, i8* %9, align 1
  %11 = sext i8 %10 to i32
  %12 = getelementptr inbounds i8, i8* %2, i64 1
  %13 = load i8, i8* %12, align 1
  %14 = sext i8 %13 to i32
  %15 = mul nsw i32 %14, %11
  %16 = add nsw i32 %15, %8
  %17 = getelementptr inbounds i8, i8* %1, i64 2
  %18 = load i8, i8* %17, align 1
  %19 = sext i8 %18 to i32
  %20 = getelementptr inbounds i8, i8* %2, i64 2
  %21 = load i8, i8* %20, align 1
  %22 = sext i8 %21 to i32
  %23 = mul nsw i32 %22, %19
  %24 = add nsw i32 %23, %16
  %25 = getelementptr inbounds i8, i8* %1, i64 3
  %26 = load i8, i8* %25, align 1
  %27 = sext i8 %26 to i32
  %28 = getelementptr inbounds i8, i8* %2, i64 3
  %29 = load i8, i8* %28, align 1
  %30 = sext i8 %29 to i32
  %31 = mul nsw i32 %30, %27
  %32 = add nsw i32 %31, %24
  store i32 %32, i32* %3, align 64
  ret void
}

define fastcc void @test_udot_v4i8(i8* noalias nocapture %0, i8* noalias nocapture readonly %1, i8* noalias nocapture readonly %2) {
; CHECK-LABEL: test_udot_v4i8:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ldr w8, [x2]
; CHECK-NEXT:    dup v0.2s, wzr
; CHECK-NEXT:    ldr w9, [x1]
; CHECK-NEXT:    fmov s1, w8
; CHECK-NEXT:    fmov s2, w9
; CHECK-NEXT:    udot v0.2s, v1.8b, v2.8b
; CHECK-NEXT:    fmov x8, d0
; CHECK-NEXT:    str w8, [x0]
; CHECK-NEXT:    ret
entry:
  %3 = bitcast i8* %0 to i32*
  %4 = load i8, i8* %1, align 1
  %5 = zext i8 %4 to i32
  %6 = load i8, i8* %2, align 1
  %7 = zext i8 %6 to i32
  %8 = mul nsw i32 %7, %5
  %9 = getelementptr inbounds i8, i8* %1, i64 1
  %10 = load i8, i8* %9, align 1
  %11 = zext i8 %10 to i32
  %12 = getelementptr inbounds i8, i8* %2, i64 1
  %13 = load i8, i8* %12, align 1
  %14 = zext i8 %13 to i32
  %15 = mul nsw i32 %14, %11
  %16 = add nsw i32 %15, %8
  %17 = getelementptr inbounds i8, i8* %1, i64 2
  %18 = load i8, i8* %17, align 1
  %19 = zext i8 %18 to i32
  %20 = getelementptr inbounds i8, i8* %2, i64 2
  %21 = load i8, i8* %20, align 1
  %22 = zext i8 %21 to i32
  %23 = mul nsw i32 %22, %19
  %24 = add nsw i32 %23, %16
  %25 = getelementptr inbounds i8, i8* %1, i64 3
  %26 = load i8, i8* %25, align 1
  %27 = zext i8 %26 to i32
  %28 = getelementptr inbounds i8, i8* %2, i64 3
  %29 = load i8, i8* %28, align 1
  %30 = zext i8 %29 to i32
  %31 = mul nsw i32 %30, %27
  %32 = add nsw i32 %31, %24
  store i32 %32, i32* %3, align 64
  ret void
}