# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -O0 -run-pass=instruction-select -verify-machineinstrs %s -global-isel-abort=1 -o - | FileCheck %s
---
name:            shl_cimm_32
legalized:       true
regBankSelected: true
body:             |
  bb.1:
    liveins: $w0

    ; CHECK-LABEL: name: shl_cimm_32
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 24, 23
    ; CHECK: $w0 = COPY [[UBFMWri]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:gpr(s32) = COPY $w0
    %1:gpr(s32) = G_CONSTANT i32 8
    %2:gpr(s32) = G_SHL %0, %1(s32)
    $w0 = COPY %2(s32)
    RET_ReallyLR implicit $w0

...
---
name:            shl_cimm_64
legalized:       true
regBankSelected: true
body:             |
  bb.1:
    liveins: $x0

    ; CHECK-LABEL: name: shl_cimm_64
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[COPY]], 56, 55
    ; CHECK: $x0 = COPY [[UBFMXri]]
    ; CHECK: RET_ReallyLR implicit $x0
    %0:gpr(s64) = COPY $x0
    %1:gpr(s64) = G_CONSTANT i64 8
    %2:gpr(s64) = G_SHL %0, %1(s64)
    $x0 = COPY %2(s64)
    RET_ReallyLR implicit $x0

...
---
name:            lshr_cimm_32
legalized:       true
regBankSelected: true
body:             |
  bb.1:
    liveins: $w0

    ; CHECK-LABEL: name: lshr_cimm_32
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 8, 31
    ; CHECK: $w0 = COPY [[UBFMWri]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:gpr(s32) = COPY $w0
    %3:gpr(s64) = G_CONSTANT i64 8
    %2:gpr(s32) = G_LSHR %0, %3(s64)
    $w0 = COPY %2(s32)
    RET_ReallyLR implicit $w0

...
---
name:            lshr_cimm_64
legalized:       true
regBankSelected: true
body:             |
  bb.1:
    liveins: $x0

    ; CHECK-LABEL: name: lshr_cimm_64
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[COPY]], 8, 63
    ; CHECK: $x0 = COPY [[UBFMXri]]
    ; CHECK: RET_ReallyLR implicit $x0
    %0:gpr(s64) = COPY $x0
    %1:gpr(s64) = G_CONSTANT i64 8
    %2:gpr(s64) = G_LSHR %0, %1(s64)
    $x0 = COPY %2(s64)
    RET_ReallyLR implicit $x0

...
---
name:            ashr_cimm_32
legalized:       true
regBankSelected: true
body:             |
  bb.1:
    liveins: $w0

    ; CHECK-LABEL: name: ashr_cimm_32
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 8, 31
    ; CHECK: $w0 = COPY [[SBFMWri]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:gpr(s32) = COPY $w0
    %3:gpr(s64) = G_CONSTANT i64 8
    %2:gpr(s32) = G_ASHR %0, %3(s64)
    $w0 = COPY %2(s32)
    RET_ReallyLR implicit $w0

...
---
name:            ashr_cimm_32_64
legalized:       true
regBankSelected: true
body:             |
  bb.1:
    liveins: $w0

    ; CHECK-LABEL: name: ashr_cimm_32_64
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -8
    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[MOVi64imm]]
    ; CHECK: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]]
    ; CHECK: $w0 = COPY [[ASRVWr]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:gpr(s32) = COPY $w0
    %3:gpr(s64) = G_CONSTANT i64 -8
    %2:gpr(s32) = G_ASHR %0, %3(s64)
    $w0 = COPY %2(s32)
    RET_ReallyLR implicit $w0

...
---
name:            lshr_cimm_32_64
legalized:       true
regBankSelected: true
body:             |
  bb.1:
    liveins: $w0

    ; CHECK-LABEL: name: lshr_cimm_32_64
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -8
    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[MOVi64imm]]
    ; CHECK: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]]
    ; CHECK: $w0 = COPY [[LSRVWr]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:gpr(s32) = COPY $w0
    %3:gpr(s64) = G_CONSTANT i64 -8
    %2:gpr(s32) = G_LSHR %0, %3(s64)
    $w0 = COPY %2(s32)
    RET_ReallyLR implicit $w0

...
---
name:            ashr_cimm_64
legalized:       true
regBankSelected: true
body:             |
  bb.1:
    liveins: $x0

    ; CHECK-LABEL: name: ashr_cimm_64
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[COPY]], 8, 63
    ; CHECK: $x0 = COPY [[SBFMXri]]
    ; CHECK: RET_ReallyLR implicit $x0
    %0:gpr(s64) = COPY $x0
    %1:gpr(s64) = G_CONSTANT i64 8
    %2:gpr(s64) = G_ASHR %0, %1(s64)
    $x0 = COPY %2(s64)
    RET_ReallyLR implicit $x0

...
---
name:            lshr_32_notimm64
legalized:       true
regBankSelected: true
body:             |
  bb.1:
    liveins: $w0

    ; CHECK-LABEL: name: lshr_32_notimm64
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 8
    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
    ; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[SUBREG_TO_REG]], 8000
    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[ANDXri]].sub_32
    ; CHECK: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]]
    ; CHECK: $w0 = COPY [[LSRVWr]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:gpr(s32) = COPY $w0
    %3:gpr(s64) = G_CONSTANT i64 8
    %4:gpr(s64) = G_AND %3, %3
    %2:gpr(s32) = G_LSHR %0, %4(s64)
    $w0 = COPY %2(s32)
    RET_ReallyLR implicit $w0

...
---
name:            ashr_32_notimm64
legalized:       true
regBankSelected: true
body:             |
  bb.1:
    liveins: $w0

    ; CHECK-LABEL: name: ashr_32_notimm64
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 8
    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
    ; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[SUBREG_TO_REG]], 8000
    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[ANDXri]].sub_32
    ; CHECK: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]]
    ; CHECK: $w0 = COPY [[ASRVWr]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:gpr(s32) = COPY $w0
    %3:gpr(s64) = G_CONSTANT i64 8
    %4:gpr(s64) = G_AND %3, %3
    %2:gpr(s32) = G_ASHR %0, %4(s64)
    $w0 = COPY %2(s32)
    RET_ReallyLR implicit $w0

...