[AArch64][SME]: Add precursory tests for D138682
Add testing files:
- bit-counting.ll
- bitselect.ll
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitselect.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitselect.ll
new file mode 100644
index 0000000..7e74d91
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitselect.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+
+target triple = "aarch64"
+
+;
+; NOTE: SVE lowering for the BSP pseudoinst is not currently implemented, so we
+; don't currently expect the code below to lower to BSL/BIT/BIF. Once
+; this is implemented, this test will be fleshed out.
+;
+
+define <8 x i32> @fixed_bitselect_v8i32(ptr %pre_cond_ptr, ptr %left_ptr, ptr %right_ptr) #0 {
+; CHECK-LABEL: fixed_bitselect_v8i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, .LCPI0_0
+; CHECK-NEXT: ldp q0, q2, [x0]
+; CHECK-NEXT: ldp q3, q1, [x1]
+; CHECK-NEXT: ldp q5, q6, [x2]
+; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI0_0]
+; CHECK-NEXT: sub z2.s, z4.s, z2.s
+; CHECK-NEXT: sub z0.s, z4.s, z0.s
+; CHECK-NEXT: bsl v0.16b, v3.16b, v5.16b
+; CHECK-NEXT: bif v1.16b, v6.16b, v2.16b
+; CHECK-NEXT: ret
+ %pre_cond = load <8 x i32>, ptr %pre_cond_ptr
+ %left = load <8 x i32>, ptr %left_ptr
+ %right = load <8 x i32>, ptr %right_ptr
+
+ %neg_cond = sub <8 x i32> zeroinitializer, %pre_cond
+ %min_cond = add <8 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
+ %left_bits_0 = and <8 x i32> %neg_cond, %left
+ %right_bits_0 = and <8 x i32> %min_cond, %right
+ %bsl0000 = or <8 x i32> %right_bits_0, %left_bits_0
+ ret <8 x i32> %bsl0000
+}
+
+attributes #0 = { "target-features"="+sve" }
