| // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s |
| |
| // --------------------------------------------------------------------------// |
| // Invalid operand (.s) |
| |
| ld1sw z23.s, p0/z, [x13, #1, MUL VL] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width |
| // CHECK-NEXT: ld1sw z23.s, p0/z, [x13, #1, MUL VL] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ld1sw z29.s, p0/z, [x3, #1, MUL VL] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width |
| // CHECK-NEXT: ld1sw z29.s, p0/z, [x3, #1, MUL VL] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| |
| // --------------------------------------------------------------------------// |
| // Immediate out of lower bound [-8, 7]. |
| |
| ld1sw z28.d, p2/z, [x28, #-9, MUL VL] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. |
| // CHECK-NEXT: ld1sw z28.d, p2/z, [x28, #-9, MUL VL] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ld1sw z27.d, p1/z, [x26, #8, MUL VL] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. |
| // CHECK-NEXT: ld1sw z27.d, p1/z, [x26, #8, MUL VL] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| |
| // --------------------------------------------------------------------------// |
| // restricted predicate has range [0, 7]. |
| |
| ld1sw z4.d, p8/z, [x11, #1, MUL VL] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) |
| // CHECK-NEXT: ld1sw z4.d, p8/z, [x11, #1, MUL VL] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| |
| // --------------------------------------------------------------------------// |
| // Invalid vector list. |
| |
| ld1sw { }, p0/z, [x1, #1, MUL VL] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected |
| // CHECK-NEXT: ld1sw { }, p0/z, [x1, #1, MUL VL] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ld1sw { z1.d, z2.d }, p0/z, [x1, #1, MUL VL] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand |
| // CHECK-NEXT: ld1sw { z1.d, z2.d }, p0/z, [x1, #1, MUL VL] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ld1sw { v0.2d }, p0/z, [x1, #1, MUL VL] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand |
| // CHECK-NEXT: ld1sw { v0.2d }, p0/z, [x1, #1, MUL VL] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| |
| // --------------------------------------------------------------------------// |
| // Invalid scalar + scalar addressing modes |
| |
| ld1sw z0.d, p0/z, [x0, x0] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' |
| // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, x0] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ld1sw z0.d, p0/z, [x0, xzr] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' |
| // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, xzr] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ld1sw z0.d, p0/z, [x0, x0, lsl #3] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' |
| // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, x0, lsl #3] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ld1sw z0.d, p0/z, [x0, w0] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' |
| // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, w0] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ld1sw z0.d, p0/z, [x0, w0, uxtw] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' |
| // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, w0, uxtw] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| |
| // --------------------------------------------------------------------------// |
| // Invalid scalar + vector addressing modes |
| |
| ld1sw z0.d, p0/z, [x0, z0.h] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand |
| // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.h] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ld1sw z0.d, p0/z, [x0, z0.s] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand |
| // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.s] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ld1sw z0.d, p0/z, [x0, z0.d, uxtw #3] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' |
| // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, uxtw #3] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ld1sw z0.d, p0/z, [x0, z0.d, lsl #3] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' |
| // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, lsl #3] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ld1sw z0.d, p0/z, [x0, z0.d, lsl] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected #imm after shift specifier |
| // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, lsl] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ld1sw z0.d, p0/z, [x0, z0.d, lsl #3] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' |
| // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, lsl #3] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ld1sw z0.d, p0/z, [x0, z0.d, sxtw #3] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' |
| // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, sxtw #3] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| |
| // --------------------------------------------------------------------------// |
| // Invalid vector + immediate addressing modes |
| |
| ld1sw z0.s, p0/z, [z0.s] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width |
| // CHECK-NEXT: ld1sw z0.s, p0/z, [z0.s] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ld1sw z0.s, p0/z, [z0.s, #4] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width |
| // CHECK-NEXT: ld1sw z0.s, p0/z, [z0.s, #4] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ld1sw z0.d, p0/z, [z0.d, #-4] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. |
| // CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #-4] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ld1sw z0.d, p0/z, [z0.d, #-1] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. |
| // CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #-1] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ld1sw z0.d, p0/z, [z0.d, #125] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. |
| // CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #125] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ld1sw z0.d, p0/z, [z0.d, #128] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. |
| // CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #128] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ld1sw z0.d, p0/z, [z0.d, #3] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. |
| // CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #3] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| |
| // --------------------------------------------------------------------------// |
| // Negative tests for instructions that are incompatible with movprfx |
| |
| movprfx z0.d, p0/z, z7.d |
| ld1sw { z0.d }, p0/z, [z0.d] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov |
| // CHECK-NEXT: ld1sw { z0.d }, p0/z, [z0.d] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| movprfx z0, z7 |
| ld1sw { z0.d }, p0/z, [z0.d] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov |
| // CHECK-NEXT: ld1sw { z0.d }, p0/z, [z0.d] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
