[AMDGPU] Reduce number of emitted S_SET_VGPR_MSB instructions (#176502)
Given a `S_SET_VGPR_MSB` instruction with `CurrentMode` and
`CurrentMask` where `CurrentMask` is a bit mask with 1 for every bit
position we set to 0 or 1 in `CurrentMode`.
We also have a new mode bitset `Mode` and a `Mask` with the bit position
we want set.
Currently we check if the difference between `Mode` and `CurrentMode`
(`Delta = Mode ^ CurrentMode`) overlaps with the bit positions we
previously set (`Delta & CurrentMask .== 0`). We then update
`CurrentMode` and `CurrentMask` accordingly.
However if bit positions differ in `Mode` and `CurrentMode` but we do
not care about these bit positions for our next instruction `(Delta &
Mask) & CurrentMask .== 0`) we can still update the previous
`S_SET_VGPR_MSB`, since we don't interfere with any of the bit positions
in `CurrentMask`
```mir
S_SET_VGPR_MSB 0x0002
$vgpr0 = V_MOV_B32_e32 $vgpr530 ; mode: 0b0000_0010 mask: 0b0000_0011
-> $vgpr1 = V_ADD_U32_e32 0x1234, $vgpr531 ; mode: 0b0000_1000 mask: 0b0000_1100
; src0 is imm so we don't care about it.
```
| | dst | src2 | src1 | src0 |
|---|---|---|---|---|
| CurrentMode | 00 | 00 | 00 | 10 |
| CurrentMask | 00 | 00 | 00 | 11 |
| Mode | 00 | 00 | 10 | 00 |
| Mask | 00 | 00 | 11 | 00 |
| Delta | 00 | 00 | 10 | 10 |
| Delta & CurrentMask | 00 | 00 | 00 | 10 |
| Delta & Mask & CurrentMask | 00 | 00 | 00 | 00 |
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