)]}'
{
  "commit": "0e9b6d6c8a111e214a3907fe97ccadf8f438d854",
  "tree": "9e605bec7a582c4746becc05b5c1fac8fa2100ac",
  "parents": [
    "b0d2b57f7e4726abc5fb6152f151c0c24625e4bf"
  ],
  "author": {
    "name": "Min-Yih Hsu",
    "email": "min.hsu@sifive.com",
    "time": "Fri Aug 15 09:22:47 2025 -0700"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Fri Aug 15 09:22:47 2025 -0700"
  },
  "message": "[IA][RISCV] Detecting gap mask from a mask assembled by interleaveN intrinsics (#153510)\n\nIf the mask of a (fixed-vector) deinterleaved load is assembled by\n`vector.interleaveN` intrinsic, any intrinsic arguments that are\nall-zeros are regarded as gaps.",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "bf128500f600501da79efbe58f801c4adf2797e8",
      "old_mode": 33188,
      "old_path": "llvm/lib/CodeGen/InterleavedAccessPass.cpp",
      "new_id": "93f6e39b56ab6443c6ad84b756c1fcd02391847e",
      "new_mode": 33188,
      "new_path": "llvm/lib/CodeGen/InterleavedAccessPass.cpp"
    },
    {
      "type": "modify",
      "old_id": "470e3095d418d40169e08f5785bb20fd19108646",
      "old_mode": 33188,
      "old_path": "llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll",
      "new_id": "c426ee7b7d2b10e0977de7a92d846fc7623cf899",
      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll"
    }
  ]
}