# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
---
name:            test_ext
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_ext
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK: $w0 = COPY [[TRUNC]](s32)
    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK: $w0 = COPY [[TRUNC1]](s32)
    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK: $w0 = COPY [[TRUNC2]](s32)
    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK: $w0 = COPY [[TRUNC3]](s32)
    ; CHECK: $x0 = COPY [[COPY]](s64)
    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
    ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
    ; CHECK: $x0 = COPY [[AND]](s64)
    ; CHECK: $x0 = COPY [[COPY]](s64)
    ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
    ; CHECK: $x0 = COPY [[SEXT_INREG]](s64)
    ; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC4]], 1
    ; CHECK: $w0 = COPY [[SEXT_INREG1]](s32)
    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
    ; CHECK: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC5]], [[C1]]
    ; CHECK: $w0 = COPY [[AND1]](s32)
    ; CHECK: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK: $w0 = COPY [[TRUNC6]](s32)
    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
    ; CHECK: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC7]], [[C2]]
    ; CHECK: $w0 = COPY [[AND2]](s32)
    ; CHECK: [[TRUNC8:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK: $w0 = COPY [[TRUNC8]](s32)
    ; CHECK: [[TRUNC9:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC9]], 16
    ; CHECK: $w0 = COPY [[SEXT_INREG2]](s32)
    ; CHECK: [[TRUNC10:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[TRUNC10]], [[C2]]
    ; CHECK: $w0 = COPY [[AND3]](s32)
    ; CHECK: [[TRUNC11:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK: $w0 = COPY [[TRUNC11]](s32)
    ; CHECK: [[TRUNC12:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK: $w0 = COPY [[TRUNC12]](s32)
    ; CHECK: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[TRUNC12]](s32)
    ; CHECK: $x0 = COPY [[FPEXT]](s64)
    ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
    ; CHECK: $w0 = COPY [[COPY1]](s32)
    ; CHECK: $w0 = COPY [[C3]](s32)
    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
    ; CHECK: $w0 = COPY [[DEF]](s32)
    %0:_(s64) = COPY $x0
    %1:_(s1) = G_TRUNC %0(s64)
    %19:_(s32) = G_ANYEXT %1(s1)
    $w0 = COPY %19(s32)
    %2:_(s8) = G_TRUNC %0(s64)
    %20:_(s32) = G_ANYEXT %2(s8)
    $w0 = COPY %20(s32)
    %3:_(s16) = G_TRUNC %0(s64)
    %21:_(s32) = G_ANYEXT %3(s16)
    $w0 = COPY %21(s32)
    %4:_(s32) = G_TRUNC %0(s64)
    $w0 = COPY %4(s32)
    %5:_(s64) = G_ANYEXT %1(s1)
    $x0 = COPY %5(s64)
    %6:_(s64) = G_ZEXT %2(s8)
    $x0 = COPY %6(s64)
    %7:_(s64) = G_ANYEXT %3(s16)
    $x0 = COPY %7(s64)
    %8:_(s64) = G_SEXT %4(s32)
    $x0 = COPY %8(s64)
    %9:_(s32) = G_SEXT %1(s1)
    $w0 = COPY %9(s32)
    %10:_(s32) = G_ZEXT %2(s8)
    $w0 = COPY %10(s32)
    %11:_(s32) = G_ANYEXT %3(s16)
    $w0 = COPY %11(s32)
    %12:_(s32) = G_ZEXT %1(s1)
    $w0 = COPY %12(s32)
    %13:_(s32) = G_ANYEXT %2(s8)
    $w0 = COPY %13(s32)
    %14:_(s32) = G_SEXT %3(s16)
    $w0 = COPY %14(s32)
    %15:_(s8) = G_ZEXT %1(s1)
    %22:_(s32) = G_ANYEXT %15(s8)
    $w0 = COPY %22(s32)
    %16:_(s16) = G_ANYEXT %2(s8)
    %23:_(s32) = G_ANYEXT %16(s16)
    $w0 = COPY %23(s32)
    %17:_(s32) = G_TRUNC %0(s64)
    $w0 = COPY %17(s32)
    %18:_(s64) = G_FPEXT %17(s32)
    $x0 = COPY %18(s64)
    %24:_(s16) = G_IMPLICIT_DEF
    %25:_(s32) = G_ZEXT %24(s16)
    $w0 = COPY %25(s32)
    %26:_(s32) = G_SEXT %24(s16)
    $w0 = COPY %26(s32)
    %27:_(s32) = G_ANYEXT %24(s16)
    $w0 = COPY %27(s32)

...
---
name:            test_anyext_anyext
body:             |
  bb.0:
    liveins: $w0

    ; CHECK-LABEL: name: test_anyext_anyext
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
    ; CHECK: $w0 = COPY [[COPY]](s32)
    %0:_(s32) = COPY $w0
    %1:_(s1) = G_TRUNC %0(s32)
    %2:_(s8) = G_ANYEXT %1(s1)
    %3:_(s32) = G_ANYEXT %2(s8)
    $w0 = COPY %3(s32)

...
---
name:            test_anyext_sext
body:             |
  bb.0:
    liveins: $w0

    ; CHECK-LABEL: name: test_anyext_sext
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
    ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
    ; CHECK: $w0 = COPY [[SEXT_INREG]](s32)
    %0:_(s32) = COPY $w0
    %1:_(s1) = G_TRUNC %0(s32)
    %2:_(s8) = G_SEXT %1(s1)
    %3:_(s32) = G_ANYEXT %2(s8)
    $w0 = COPY %3(s32)

...
---
name:            test_anyext_zext
body:             |
  bb.0:
    liveins: $w0

    ; CHECK-LABEL: name: test_anyext_zext
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
    ; CHECK: $w0 = COPY [[AND]](s32)
    %0:_(s32) = COPY $w0
    %1:_(s1) = G_TRUNC %0(s32)
    %2:_(s8) = G_ZEXT %1(s1)
    %3:_(s32) = G_ANYEXT %2(s8)
    $w0 = COPY %3(s32)

...
---
name:            test_zext_v8s16_from_v8s8
alignment:       4
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0
    ; CHECK-LABEL: name: test_zext_v8s16_from_v8s8
    ; CHECK: liveins: $d0
    ; CHECK: [[COPY:%[0-9]+]]:fpr(<8 x s8>) = COPY $d0
    ; CHECK: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)
    ; CHECK: $q0 = COPY [[ZEXT]](<8 x s16>)
    ; CHECK: RET_ReallyLR implicit $q0
    %1:fpr(<8 x s8>) = COPY $d0
    %2:_(<8 x s16>) = G_ZEXT %1(<8 x s8>)
    $q0 = COPY %2(<8 x s16>)
    RET_ReallyLR implicit $q0

...
---
name:            test_sext_v8s16_from_v8s8
alignment:       4
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0
    ; CHECK-LABEL: name: test_sext_v8s16_from_v8s8
    ; CHECK: liveins: $d0
    ; CHECK: [[COPY:%[0-9]+]]:fpr(<8 x s8>) = COPY $d0
    ; CHECK: [[SEXT:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)
    ; CHECK: $q0 = COPY [[SEXT]](<8 x s16>)
    ; CHECK: RET_ReallyLR implicit $q0
    %1:fpr(<8 x s8>) = COPY $d0
    %2:_(<8 x s16>) = G_SEXT %1(<8 x s8>)
    $q0 = COPY %2(<8 x s16>)
    RET_ReallyLR implicit $q0

...
---
name:            test_anyext_v8s16_from_v8s8
alignment:       4
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0
    ; CHECK-LABEL: name: test_anyext_v8s16_from_v8s8
    ; CHECK: liveins: $d0
    ; CHECK: [[COPY:%[0-9]+]]:fpr(<8 x s8>) = COPY $d0
    ; CHECK: [[ANYEXT:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT [[COPY]](<8 x s8>)
    ; CHECK: $q0 = COPY [[ANYEXT]](<8 x s16>)
    ; CHECK: RET_ReallyLR implicit $q0
    %1:fpr(<8 x s8>) = COPY $d0
    %2:_(<8 x s16>) = G_ANYEXT %1(<8 x s8>)
    $q0 = COPY %2(<8 x s16>)
    RET_ReallyLR implicit $q0

...
---
name:            test_zext_v4s32_from_v4s16
alignment:       4
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: test_zext_v4s32_from_v4s16
    ; CHECK: liveins: $d0
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
    ; CHECK: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[COPY]](<4 x s16>)
    ; CHECK: $q0 = COPY [[ZEXT]](<4 x s32>)
    ; CHECK: RET_ReallyLR implicit $q0
    %0:_(<4 x s16>) = COPY $d0
    %1:_(<4 x s32>) = G_ZEXT %0(<4 x s16>)
    $q0 = COPY %1(<4 x s32>)
    RET_ReallyLR implicit $q0

...
---
name:            test_sext_v4s32_from_v4s16
alignment:       4
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: test_sext_v4s32_from_v4s16
    ; CHECK: liveins: $d0
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
    ; CHECK: [[SEXT:%[0-9]+]]:_(<4 x s32>) = G_SEXT [[COPY]](<4 x s16>)
    ; CHECK: $q0 = COPY [[SEXT]](<4 x s32>)
    ; CHECK: RET_ReallyLR implicit $q0
    %0:_(<4 x s16>) = COPY $d0
    %1:_(<4 x s32>) = G_SEXT %0(<4 x s16>)
    $q0 = COPY %1(<4 x s32>)
    RET_ReallyLR implicit $q0

...
---
name:            test_anyext_v4s32_from_v4s16
alignment:       4
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: test_anyext_v4s32_from_v4s16
    ; CHECK: liveins: $d0
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
    ; CHECK: [[ANYEXT:%[0-9]+]]:_(<4 x s32>) = G_ANYEXT [[COPY]](<4 x s16>)
    ; CHECK: $q0 = COPY [[ANYEXT]](<4 x s32>)
    ; CHECK: RET_ReallyLR implicit $q0
    %0:_(<4 x s16>) = COPY $d0
    %1:_(<4 x s32>) = G_ANYEXT %0(<4 x s16>)
    $q0 = COPY %1(<4 x s32>)
    RET_ReallyLR implicit $q0

...
---
name:            test_zext_v2s64_from_v2s32
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: test_zext_v2s64_from_v2s32
    ; CHECK: liveins: $d0
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
    ; CHECK: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY]](<2 x s32>)
    ; CHECK: $q0 = COPY [[ZEXT]](<2 x s64>)
    ; CHECK: RET_ReallyLR implicit $q0
    %0:_(<2 x s32>) = COPY $d0
    %1:_(<2 x s64>) = G_ZEXT %0(<2 x s32>)
    $q0 = COPY %1(<2 x s64>)
    RET_ReallyLR implicit $q0

...
---
name:            test_sext_v2s64_from_v2s32
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: test_sext_v2s64_from_v2s32
    ; CHECK: liveins: $d0
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
    ; CHECK: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY]](<2 x s32>)
    ; CHECK: $q0 = COPY [[SEXT]](<2 x s64>)
    ; CHECK: RET_ReallyLR implicit $q0
    %0:_(<2 x s32>) = COPY $d0
    %1:_(<2 x s64>) = G_SEXT %0(<2 x s32>)
    $q0 = COPY %1(<2 x s64>)
    RET_ReallyLR implicit $q0

...
---
name:            test_anyext_v2s64_from_v2s32
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: test_anyext_v2s64_from_v2s32
    ; CHECK: liveins: $d0
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
    ; CHECK: [[ANYEXT:%[0-9]+]]:_(<2 x s64>) = G_ANYEXT [[COPY]](<2 x s32>)
    ; CHECK: $q0 = COPY [[ANYEXT]](<2 x s64>)
    ; CHECK: RET_ReallyLR implicit $q0
    %0:_(<2 x s32>) = COPY $d0
    %1:_(<2 x s64>) = G_ANYEXT %0(<2 x s32>)
    $q0 = COPY %1(<2 x s64>)
    RET_ReallyLR implicit $q0

...