[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#66295)
This will make it easy for callers to see issues with and fix up calls
to createTargetMachine after a future change to the params of
TargetMachine.
This matches other nearby enums.
For downstream users, this should be a fairly straightforward
replacement,
e.g. s/CodeGenOpt::Aggressive/CodeGenOptLevel::Aggressive
or s/CGFT_/CodeGenFileType::
diff --git a/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
index c43ca25..b25a38b 100644
--- a/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
@@ -1537,8 +1537,8 @@
}
FPO |= FrameProcedureOptions(uint32_t(CurFn->EncodedLocalFramePtrReg) << 14U);
FPO |= FrameProcedureOptions(uint32_t(CurFn->EncodedParamFramePtrReg) << 16U);
- if (Asm->TM.getOptLevel() != CodeGenOpt::None &&
- !GV.hasOptSize() && !GV.hasOptNone())
+ if (Asm->TM.getOptLevel() != CodeGenOptLevel::None && !GV.hasOptSize() &&
+ !GV.hasOptNone())
FPO |= FrameProcedureOptions::OptimizedForSpeed;
if (GV.hasProfileData()) {
FPO |= FrameProcedureOptions::ValidProfileCounts;
diff --git a/llvm/lib/CodeGen/CommandFlags.cpp b/llvm/lib/CodeGen/CommandFlags.cpp
index c34a52a..59bd6da 100644
--- a/llvm/lib/CodeGen/CommandFlags.cpp
+++ b/llvm/lib/CodeGen/CommandFlags.cpp
@@ -180,15 +180,15 @@
CGBINDOPT(ExceptionModel);
static cl::opt<CodeGenFileType> FileType(
- "filetype", cl::init(CGFT_AssemblyFile),
+ "filetype", cl::init(CodeGenFileType::AssemblyFile),
cl::desc(
"Choose a file type (not all types are supported by all targets):"),
- cl::values(
- clEnumValN(CGFT_AssemblyFile, "asm", "Emit an assembly ('.s') file"),
- clEnumValN(CGFT_ObjectFile, "obj",
- "Emit a native object ('.o') file"),
- clEnumValN(CGFT_Null, "null",
- "Emit nothing, for performance testing")));
+ cl::values(clEnumValN(CodeGenFileType::AssemblyFile, "asm",
+ "Emit an assembly ('.s') file"),
+ clEnumValN(CodeGenFileType::ObjectFile, "obj",
+ "Emit a native object ('.o') file"),
+ clEnumValN(CodeGenFileType::Null, "null",
+ "Emit nothing, for performance testing")));
CGBINDOPT(FileType);
static cl::opt<FramePointerKind> FramePointerUsage(
diff --git a/llvm/lib/CodeGen/DwarfEHPrepare.cpp b/llvm/lib/CodeGen/DwarfEHPrepare.cpp
index 32c94de..1d02f53 100644
--- a/llvm/lib/CodeGen/DwarfEHPrepare.cpp
+++ b/llvm/lib/CodeGen/DwarfEHPrepare.cpp
@@ -54,7 +54,7 @@
namespace {
class DwarfEHPrepare {
- CodeGenOpt::Level OptLevel;
+ CodeGenOptLevel OptLevel;
Function &F;
const TargetLowering &TLI;
@@ -78,7 +78,7 @@
bool InsertUnwindResumeCalls();
public:
- DwarfEHPrepare(CodeGenOpt::Level OptLevel_, Function &F_,
+ DwarfEHPrepare(CodeGenOptLevel OptLevel_, Function &F_,
const TargetLowering &TLI_, DomTreeUpdater *DTU_,
const TargetTransformInfo *TTI_, const Triple &TargetTriple_)
: OptLevel(OptLevel_), F(F_), TLI(TLI_), DTU(DTU_), TTI(TTI_),
@@ -194,7 +194,7 @@
LLVMContext &Ctx = F.getContext();
size_t ResumesLeft = Resumes.size();
- if (OptLevel != CodeGenOpt::None) {
+ if (OptLevel != CodeGenOptLevel::None) {
ResumesLeft = pruneUnreachableResumes(Resumes, CleanupLPads);
#if LLVM_ENABLE_STATS
unsigned NumRemainingLPs = 0;
@@ -309,7 +309,7 @@
return Changed;
}
-static bool prepareDwarfEH(CodeGenOpt::Level OptLevel, Function &F,
+static bool prepareDwarfEH(CodeGenOptLevel OptLevel, Function &F,
const TargetLowering &TLI, DominatorTree *DT,
const TargetTransformInfo *TTI,
const Triple &TargetTriple) {
@@ -324,12 +324,12 @@
class DwarfEHPrepareLegacyPass : public FunctionPass {
- CodeGenOpt::Level OptLevel;
+ CodeGenOptLevel OptLevel;
public:
static char ID; // Pass identification, replacement for typeid.
- DwarfEHPrepareLegacyPass(CodeGenOpt::Level OptLevel = CodeGenOpt::Default)
+ DwarfEHPrepareLegacyPass(CodeGenOptLevel OptLevel = CodeGenOptLevel::Default)
: FunctionPass(ID), OptLevel(OptLevel) {}
bool runOnFunction(Function &F) override {
@@ -340,7 +340,7 @@
const TargetTransformInfo *TTI = nullptr;
if (auto *DTWP = getAnalysisIfAvailable<DominatorTreeWrapperPass>())
DT = &DTWP->getDomTree();
- if (OptLevel != CodeGenOpt::None) {
+ if (OptLevel != CodeGenOptLevel::None) {
if (!DT)
DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
TTI = &getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
@@ -351,7 +351,7 @@
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<TargetPassConfig>();
AU.addRequired<TargetTransformInfoWrapperPass>();
- if (OptLevel != CodeGenOpt::None) {
+ if (OptLevel != CodeGenOptLevel::None) {
AU.addRequired<DominatorTreeWrapperPass>();
AU.addRequired<TargetTransformInfoWrapperPass>();
}
@@ -375,6 +375,6 @@
INITIALIZE_PASS_END(DwarfEHPrepareLegacyPass, DEBUG_TYPE,
"Prepare DWARF exceptions", false, false)
-FunctionPass *llvm::createDwarfEHPass(CodeGenOpt::Level OptLevel) {
+FunctionPass *llvm::createDwarfEHPass(CodeGenOptLevel OptLevel) {
return new DwarfEHPrepareLegacyPass(OptLevel);
}
diff --git a/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp b/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
index d966fae..ca4d098 100644
--- a/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
@@ -76,9 +76,9 @@
}
std::unique_ptr<CSEConfigBase>
-llvm::getStandardCSEConfigForOpt(CodeGenOpt::Level Level) {
+llvm::getStandardCSEConfigForOpt(CodeGenOptLevel Level) {
std::unique_ptr<CSEConfigBase> Config;
- if (Level == CodeGenOpt::None)
+ if (Level == CodeGenOptLevel::None)
Config = std::make_unique<CSEConfigConstantOnly>();
else
Config = std::make_unique<CSEConfigFull>();
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 41a0295..3e2a744 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -127,7 +127,7 @@
ORE.emit(R);
}
-IRTranslator::IRTranslator(CodeGenOpt::Level optlevel)
+IRTranslator::IRTranslator(CodeGenOptLevel optlevel)
: MachineFunctionPass(ID), OptLevel(optlevel) {}
#ifndef NDEBUG
@@ -173,7 +173,7 @@
AU.addRequired<TargetPassConfig>();
AU.addRequired<GISelCSEAnalysisWrapperPass>();
AU.addRequired<AssumptionCacheTracker>();
- if (OptLevel != CodeGenOpt::None) {
+ if (OptLevel != CodeGenOptLevel::None) {
AU.addRequired<BranchProbabilityInfoWrapperPass>();
AU.addRequired<AAResultsWrapperPass>();
}
@@ -578,7 +578,8 @@
if (BrInst.isUnconditional()) {
// If the unconditional target is the layout successor, fallthrough.
- if (OptLevel == CodeGenOpt::None || !CurMBB.isLayoutSuccessor(Succ0MBB))
+ if (OptLevel == CodeGenOptLevel::None ||
+ !CurMBB.isLayoutSuccessor(Succ0MBB))
MIRBuilder.buildBr(*Succ0MBB);
// Link successors.
@@ -1974,7 +1975,7 @@
case Intrinsic::lifetime_start:
case Intrinsic::lifetime_end: {
// No stack colouring in O0, discard region information.
- if (MF->getTarget().getOptLevel() == CodeGenOpt::None)
+ if (MF->getTarget().getOptLevel() == CodeGenOptLevel::None)
return true;
unsigned Op = ID == Intrinsic::lifetime_start ? TargetOpcode::LIFETIME_START
@@ -3488,7 +3489,7 @@
ORE = std::make_unique<OptimizationRemarkEmitter>(&F);
const TargetMachine &TM = MF->getTarget();
TM.resetTargetOptions(F);
- EnableOpts = OptLevel != CodeGenOpt::None && !skipFunction(F);
+ EnableOpts = OptLevel != CodeGenOptLevel::None && !skipFunction(F);
FuncInfo.MF = MF;
if (EnableOpts) {
AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
diff --git a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
index 9bbef11..75f1fbc 100644
--- a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
@@ -58,21 +58,21 @@
"Select target instructions out of generic instructions",
false, false)
-InstructionSelect::InstructionSelect(CodeGenOpt::Level OL)
+InstructionSelect::InstructionSelect(CodeGenOptLevel OL)
: MachineFunctionPass(ID), OptLevel(OL) {}
// In order not to crash when calling getAnalysis during testing with -run-pass
// we use the default opt level here instead of None, so that the addRequired()
// calls are made in getAnalysisUsage().
InstructionSelect::InstructionSelect()
- : MachineFunctionPass(ID), OptLevel(CodeGenOpt::Default) {}
+ : MachineFunctionPass(ID), OptLevel(CodeGenOptLevel::Default) {}
void InstructionSelect::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<TargetPassConfig>();
AU.addRequired<GISelKnownBitsAnalysis>();
AU.addPreserved<GISelKnownBitsAnalysis>();
- if (OptLevel != CodeGenOpt::None) {
+ if (OptLevel != CodeGenOptLevel::None) {
AU.addRequired<ProfileSummaryInfoWrapperPass>();
LazyBlockFrequencyInfoPass::getLazyBFIAnalysisUsage(AU);
}
@@ -91,13 +91,13 @@
const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
InstructionSelector *ISel = MF.getSubtarget().getInstructionSelector();
- CodeGenOpt::Level OldOptLevel = OptLevel;
+ CodeGenOptLevel OldOptLevel = OptLevel;
auto RestoreOptLevel = make_scope_exit([=]() { OptLevel = OldOptLevel; });
- OptLevel = MF.getFunction().hasOptNone() ? CodeGenOpt::None
+ OptLevel = MF.getFunction().hasOptNone() ? CodeGenOptLevel::None
: MF.getTarget().getOptLevel();
GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
- if (OptLevel != CodeGenOpt::None) {
+ if (OptLevel != CodeGenOptLevel::None) {
PSI = &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
if (PSI && PSI->hasProfileSummary())
BFI = &getAnalysis<LazyBlockFrequencyInfoPass>().getBFI();
diff --git a/llvm/lib/CodeGen/LLVMTargetMachine.cpp b/llvm/lib/CodeGen/LLVMTargetMachine.cpp
index d02ec1d..7ec8390 100644
--- a/llvm/lib/CodeGen/LLVMTargetMachine.cpp
+++ b/llvm/lib/CodeGen/LLVMTargetMachine.cpp
@@ -87,7 +87,7 @@
const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
- CodeGenOpt::Level OL)
+ CodeGenOptLevel OL)
: TargetMachine(T, DataLayoutString, TT, CPU, FS, Options) {
this->RM = RM;
this->CMModel = CM;
@@ -156,7 +156,7 @@
std::unique_ptr<MCStreamer> AsmStreamer;
switch (FileType) {
- case CGFT_AssemblyFile: {
+ case CodeGenFileType::AssemblyFile: {
MCInstPrinter *InstPrinter = getTarget().createMCInstPrinter(
getTargetTriple(), MAI.getAssemblerDialect(), MAI, MII, MRI);
@@ -188,7 +188,7 @@
AsmStreamer.reset(S);
break;
}
- case CGFT_ObjectFile: {
+ case CodeGenFileType::ObjectFile: {
// Create the code emitter for the target if it exists. If not, .o file
// emission fails.
MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, Context);
@@ -211,7 +211,7 @@
/*DWARFMustBeAtTheEnd*/ true));
break;
}
- case CGFT_Null:
+ case CodeGenFileType::Null:
// The Null output is intended for use for performance analysis and testing,
// not real users.
AsmStreamer.reset(getTarget().createNullStreamer(Context));
@@ -238,7 +238,7 @@
return true;
} else {
// MIR printing is redundant with -filetype=null.
- if (FileType != CGFT_Null)
+ if (FileType != CodeGenFileType::Null)
PM.add(createPrintMIRPass(Out));
}
diff --git a/llvm/lib/CodeGen/MachineBlockPlacement.cpp b/llvm/lib/CodeGen/MachineBlockPlacement.cpp
index 912e9ec..24f0197 100644
--- a/llvm/lib/CodeGen/MachineBlockPlacement.cpp
+++ b/llvm/lib/CodeGen/MachineBlockPlacement.cpp
@@ -3376,7 +3376,7 @@
TargetPassConfig *PassConfig = &getAnalysis<TargetPassConfig>();
// For aggressive optimization, we can adjust some thresholds to be less
// conservative.
- if (PassConfig->getOptLevel() >= CodeGenOpt::Aggressive) {
+ if (PassConfig->getOptLevel() >= CodeGenOptLevel::Aggressive) {
// At O3 we should be more willing to copy blocks for tail duplication. This
// increases size pressure, so we only do it at O3
// Do this unless only the regular threshold is explicitly set.
@@ -3388,7 +3388,7 @@
// If there's no threshold provided through options, query the target
// information for a threshold instead.
if (TailDupPlacementThreshold.getNumOccurrences() == 0 &&
- (PassConfig->getOptLevel() < CodeGenOpt::Aggressive ||
+ (PassConfig->getOptLevel() < CodeGenOptLevel::Aggressive ||
TailDupPlacementAggressiveThreshold.getNumOccurrences() == 0))
TailDupSize = TII->getTailDuplicateSize(PassConfig->getOptLevel());
diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp
index e1f9488..1f14546 100644
--- a/llvm/lib/CodeGen/MachineFunction.cpp
+++ b/llvm/lib/CodeGen/MachineFunction.cpp
@@ -1206,7 +1206,7 @@
// have optimized code inlined into this unoptimized code, however with
// fewer and less aggressive optimizations happening, coverage and accuracy
// should not suffer.
- if (getTarget().getOptLevel() == CodeGenOpt::None)
+ if (getTarget().getOptLevel() == CodeGenOptLevel::None)
return false;
// Don't use instr-ref if this function is marked optnone.
diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp
index 170008a..ffd70a2 100644
--- a/llvm/lib/CodeGen/PostRASchedulerList.cpp
+++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp
@@ -101,7 +101,7 @@
private:
bool enablePostRAScheduler(
- const TargetSubtargetInfo &ST, CodeGenOpt::Level OptLevel,
+ const TargetSubtargetInfo &ST, CodeGenOptLevel OptLevel,
TargetSubtargetInfo::AntiDepBreakMode &Mode,
TargetSubtargetInfo::RegClassVector &CriticalPathRCs) const;
};
@@ -260,8 +260,7 @@
#endif
bool PostRAScheduler::enablePostRAScheduler(
- const TargetSubtargetInfo &ST,
- CodeGenOpt::Level OptLevel,
+ const TargetSubtargetInfo &ST, CodeGenOptLevel OptLevel,
TargetSubtargetInfo::AntiDepBreakMode &Mode,
TargetSubtargetInfo::RegClassVector &CriticalPathRCs) const {
Mode = ST.getAntiDepBreakMode();
diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
index 6c8be5c..9514a08 100644
--- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -1083,7 +1083,7 @@
MaxAlign);
// Give the targets a chance to order the objects the way they like it.
- if (MF.getTarget().getOptLevel() != CodeGenOpt::None &&
+ if (MF.getTarget().getOptLevel() != CodeGenOptLevel::None &&
MF.getTarget().Options.StackSymbolOrdering)
TFI.orderFrameObjects(MF, ObjectsToAllocate);
@@ -1093,7 +1093,7 @@
// optimizing.
BitVector StackBytesFree;
if (!ObjectsToAllocate.empty() &&
- MF.getTarget().getOptLevel() != CodeGenOpt::None &&
+ MF.getTarget().getOptLevel() != CodeGenOptLevel::None &&
MFI.getStackProtectorIndex() < 0 && TFI.enableStackSlotScavenging(MF))
computeFreeStackSlots(MFI, StackGrowsDown, MinCSFrameIndex, MaxCSFrameIndex,
FixedCSEnd, StackBytesFree);
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index cd34c0d..c641222 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -149,7 +149,7 @@
const TargetLowering &TLI;
const SelectionDAGTargetInfo *STI;
CombineLevel Level = BeforeLegalizeTypes;
- CodeGenOpt::Level OptLevel;
+ CodeGenOptLevel OptLevel;
bool LegalDAG = false;
bool LegalOperations = false;
bool LegalTypes = false;
@@ -242,7 +242,7 @@
SDValue visit(SDNode *N);
public:
- DAGCombiner(SelectionDAG &D, AliasAnalysis *AA, CodeGenOpt::Level OL)
+ DAGCombiner(SelectionDAG &D, AliasAnalysis *AA, CodeGenOptLevel OL)
: DAG(D), TLI(D.getTargetLoweringInfo()),
STI(D.getSubtarget().getSelectionDAGInfo()), OptLevel(OL), AA(AA) {
ForCodeSize = DAG.shouldOptForSize();
@@ -2153,7 +2153,7 @@
}
// Don't simplify token factors if optnone.
- if (OptLevel == CodeGenOpt::None)
+ if (OptLevel == CodeGenOptLevel::None)
return SDValue();
// Don't simplify the token factor if the node itself has too many operands.
@@ -8789,7 +8789,7 @@
// TODO: If there is evidence that running this later would help, this
// limitation could be removed. Legality checks may need to be added
// for the created store and optional bswap/rotate.
- if (LegalOperations || OptLevel == CodeGenOpt::None)
+ if (LegalOperations || OptLevel == CodeGenOptLevel::None)
return SDValue();
// We only handle merging simple stores of 1-4 bytes.
@@ -18178,7 +18178,7 @@
}
SDValue DAGCombiner::ForwardStoreValueToDirectLoad(LoadSDNode *LD) {
- if (OptLevel == CodeGenOpt::None || !LD->isSimple())
+ if (OptLevel == CodeGenOptLevel::None || !LD->isSimple())
return SDValue();
SDValue Chain = LD->getOperand(0);
int64_t Offset;
@@ -18378,7 +18378,8 @@
return V;
// Try to infer better alignment information than the load already has.
- if (OptLevel != CodeGenOpt::None && LD->isUnindexed() && !LD->isAtomic()) {
+ if (OptLevel != CodeGenOptLevel::None && LD->isUnindexed() &&
+ !LD->isAtomic()) {
if (MaybeAlign Alignment = DAG.InferPtrAlign(Ptr)) {
if (*Alignment > LD->getAlign() &&
isAligned(*Alignment, LD->getSrcValueOffset())) {
@@ -20401,7 +20402,7 @@
}
bool DAGCombiner::mergeConsecutiveStores(StoreSDNode *St) {
- if (OptLevel == CodeGenOpt::None || !EnableStoreMerging)
+ if (OptLevel == CodeGenOptLevel::None || !EnableStoreMerging)
return false;
// TODO: Extend this function to merge stores of scalable vectors.
@@ -20680,7 +20681,8 @@
return Chain;
// Try to infer better alignment information than the store already has.
- if (OptLevel != CodeGenOpt::None && ST->isUnindexed() && !ST->isAtomic()) {
+ if (OptLevel != CodeGenOptLevel::None && ST->isUnindexed() &&
+ !ST->isAtomic()) {
if (MaybeAlign Alignment = DAG.InferPtrAlign(Ptr)) {
if (*Alignment > ST->getAlign() &&
isAligned(*Alignment, ST->getSrcValueOffset())) {
@@ -20796,7 +20798,7 @@
if (StoreSDNode *ST1 = dyn_cast<StoreSDNode>(Chain)) {
if (ST->isUnindexed() && ST->isSimple() &&
ST1->isUnindexed() && ST1->isSimple()) {
- if (OptLevel != CodeGenOpt::None && ST1->getBasePtr() == Ptr &&
+ if (OptLevel != CodeGenOptLevel::None && ST1->getBasePtr() == Ptr &&
ST1->getValue() == Value && ST->getMemoryVT() == ST1->getMemoryVT() &&
ST->getAddressSpace() == ST1->getAddressSpace()) {
// If this is a store followed by a store with the same value to the
@@ -20804,7 +20806,7 @@
return Chain;
}
- if (OptLevel != CodeGenOpt::None && ST1->hasOneUse() &&
+ if (OptLevel != CodeGenOptLevel::None && ST1->hasOneUse() &&
!ST1->getBasePtr().isUndef() &&
ST->getAddressSpace() == ST1->getAddressSpace()) {
// If we consider two stores and one smaller in size is a scalable
@@ -20967,7 +20969,7 @@
/// }
///
SDValue DAGCombiner::splitMergedValStore(StoreSDNode *ST) {
- if (OptLevel == CodeGenOpt::None)
+ if (OptLevel == CodeGenOptLevel::None)
return SDValue();
// Can't change the number of memory accesses for a volatile store or break
@@ -27540,7 +27542,7 @@
/// Walk up chain skipping non-aliasing memory nodes, looking for a better chain
/// (aliasing node.)
SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
- if (OptLevel == CodeGenOpt::None)
+ if (OptLevel == CodeGenOptLevel::None)
return OldChain;
// Ops for replacing token factor.
@@ -27697,7 +27699,7 @@
}
bool DAGCombiner::findBetterNeighborChains(StoreSDNode *St) {
- if (OptLevel == CodeGenOpt::None)
+ if (OptLevel == CodeGenOptLevel::None)
return false;
const BaseIndexOffset BasePtr = BaseIndexOffset::match(St, DAG);
@@ -27725,7 +27727,7 @@
/// This is the entry point for the file.
void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis *AA,
- CodeGenOpt::Level OptLevel) {
+ CodeGenOptLevel OptLevel) {
/// This is the main entry point to this class.
DAGCombiner(*this, AA, OptLevel).Run(Level);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
index 5abfe16..ab4c33c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
@@ -808,12 +808,12 @@
// Public Constructor Functions
//===----------------------------------------------------------------------===//
-llvm::ScheduleDAGSDNodes *
-llvm::createFastDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
+llvm::ScheduleDAGSDNodes *llvm::createFastDAGScheduler(SelectionDAGISel *IS,
+ CodeGenOptLevel) {
return new ScheduleDAGFast(*IS->MF);
}
-llvm::ScheduleDAGSDNodes *
-llvm::createDAGLinearizer(SelectionDAGISel *IS, CodeGenOpt::Level) {
+llvm::ScheduleDAGSDNodes *llvm::createDAGLinearizer(SelectionDAGISel *IS,
+ CodeGenOptLevel) {
return new ScheduleDAGLinearize(*IS->MF);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 4ca3385..36f68e9 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -188,10 +188,9 @@
public:
ScheduleDAGRRList(MachineFunction &mf, bool needlatency,
SchedulingPriorityQueue *availqueue,
- CodeGenOpt::Level OptLevel)
- : ScheduleDAGSDNodes(mf),
- NeedLatency(needlatency), AvailableQueue(availqueue),
- Topo(SUnits, nullptr) {
+ CodeGenOptLevel OptLevel)
+ : ScheduleDAGSDNodes(mf), NeedLatency(needlatency),
+ AvailableQueue(availqueue), Topo(SUnits, nullptr) {
const TargetSubtargetInfo &STI = mf.getSubtarget();
if (DisableSchedCycles || !NeedLatency)
HazardRec = new ScheduleHazardRecognizer();
@@ -3150,9 +3149,8 @@
// Public Constructor Functions
//===----------------------------------------------------------------------===//
-ScheduleDAGSDNodes *
-llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
- CodeGenOpt::Level OptLevel) {
+ScheduleDAGSDNodes *llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
+ CodeGenOptLevel OptLevel) {
const TargetSubtargetInfo &STI = IS->MF->getSubtarget();
const TargetInstrInfo *TII = STI.getInstrInfo();
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
@@ -3166,7 +3164,7 @@
ScheduleDAGSDNodes *
llvm::createSourceListDAGScheduler(SelectionDAGISel *IS,
- CodeGenOpt::Level OptLevel) {
+ CodeGenOptLevel OptLevel) {
const TargetSubtargetInfo &STI = IS->MF->getSubtarget();
const TargetInstrInfo *TII = STI.getInstrInfo();
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
@@ -3180,7 +3178,7 @@
ScheduleDAGSDNodes *
llvm::createHybridListDAGScheduler(SelectionDAGISel *IS,
- CodeGenOpt::Level OptLevel) {
+ CodeGenOptLevel OptLevel) {
const TargetSubtargetInfo &STI = IS->MF->getSubtarget();
const TargetInstrInfo *TII = STI.getInstrInfo();
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
@@ -3194,9 +3192,8 @@
return SD;
}
-ScheduleDAGSDNodes *
-llvm::createILPListDAGScheduler(SelectionDAGISel *IS,
- CodeGenOpt::Level OptLevel) {
+ScheduleDAGSDNodes *llvm::createILPListDAGScheduler(SelectionDAGISel *IS,
+ CodeGenOptLevel OptLevel) {
const TargetSubtargetInfo &STI = IS->MF->getSubtarget();
const TargetInstrInfo *TII = STI.getInstrInfo();
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp
index 1ba1fd6..ae42a87 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp
@@ -265,7 +265,7 @@
//===----------------------------------------------------------------------===//
/// createVLIWDAGScheduler - This creates a top-down list scheduler.
-ScheduleDAGSDNodes *
-llvm::createVLIWDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
+ScheduleDAGSDNodes *llvm::createVLIWDAGScheduler(SelectionDAGISel *IS,
+ CodeGenOptLevel) {
return new ScheduleDAGVLIW(*IS->MF, IS->AA, new ResourcePriorityQueue(IS));
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 8d6d328..60f4ea7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1303,9 +1303,9 @@
}
// EntryNode could meaningfully have debug info if we can find it...
-SelectionDAG::SelectionDAG(const TargetMachine &tm, CodeGenOpt::Level OL)
- : TM(tm), OptLevel(OL),
- EntryNode(ISD::EntryToken, 0, DebugLoc(), getVTList(MVT::Other, MVT::Glue)),
+SelectionDAG::SelectionDAG(const TargetMachine &tm, CodeGenOptLevel OL)
+ : TM(tm), OptLevel(OL), EntryNode(ISD::EntryToken, 0, DebugLoc(),
+ getVTList(MVT::Other, MVT::Glue)),
Root(getEntryNode()) {
InsertNode(&EntryNode);
DbgInfo = new SDDbgInfo();
@@ -10291,7 +10291,7 @@
/// For IROrder, we keep the smaller of the two
SDNode *SelectionDAG::UpdateSDLocOnMergeSDNode(SDNode *N, const SDLoc &OLoc) {
DebugLoc NLoc = N->getDebugLoc();
- if (NLoc && OptLevel == CodeGenOpt::None && OLoc.getDebugLoc() != NLoc) {
+ if (NLoc && OptLevel == CodeGenOptLevel::None && OLoc.getDebugLoc() != NLoc) {
N->setDebugLoc(DebugLoc());
}
unsigned Order = std::min(N->getIROrder(), OLoc.getIROrder());
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 720fc49..7a85f19 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -1822,7 +1822,7 @@
// If this is not a fall-through branch or optimizations are switched off,
// emit the branch.
if (TargetMBB != NextBlock(FuncInfo.MBB) ||
- TM.getOptLevel() == CodeGenOpt::None)
+ TM.getOptLevel() == CodeGenOptLevel::None)
DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
getControlRoot(), DAG.getBasicBlock(TargetMBB)));
return;
@@ -2478,7 +2478,8 @@
// If this is not a fall-through branch or optimizations are switched off,
// emit the branch.
- if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None) {
+ if (Succ0MBB != NextBlock(BrMBB) ||
+ TM.getOptLevel() == CodeGenOptLevel::None) {
auto Br = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
getControlRoot(), DAG.getBasicBlock(Succ0MBB));
setValue(&I, Br);
@@ -7107,7 +7108,7 @@
case Intrinsic::lifetime_end: {
bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
// Stack coloring is not enabled in O0, discard region information.
- if (TM.getOptLevel() == CodeGenOpt::None)
+ if (TM.getOptLevel() == CodeGenOptLevel::None)
return;
const int64_t ObjectSize =
@@ -11293,7 +11294,7 @@
}
}
- if (TM.getOptLevel() != CodeGenOpt::None) {
+ if (TM.getOptLevel() != CodeGenOptLevel::None) {
// Here, we order cases by probability so the most likely case will be
// checked first. However, two clusters can have the same probability in
// which case their relative ordering is non-deterministic. So we use Low
@@ -11651,7 +11652,7 @@
MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
// Don't perform if there is only one cluster or optimizing for size.
if (SwitchPeelThreshold > 100 || !FuncInfo.BPI || Clusters.size() < 2 ||
- TM.getOptLevel() == CodeGenOpt::None ||
+ TM.getOptLevel() == CodeGenOptLevel::None ||
SwitchMBB->getParent()->getFunction().hasMinSize())
return SwitchMBB;
@@ -11773,7 +11774,7 @@
SwitchWorkListItem W = WorkList.pop_back_val();
unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
- if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None &&
+ if (NumClusters > 3 && TM.getOptLevel() != CodeGenOptLevel::None &&
!DefaultMBB->getParent()->getFunction().hasMinSize()) {
// For optimized builds, lower large range as a balanced binary tree.
splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
index 55a63ec..ec23445b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
@@ -295,10 +295,10 @@
LLVMContext *Context = nullptr;
SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
- SwiftErrorValueTracking &swifterror, CodeGenOpt::Level ol)
+ SwiftErrorValueTracking &swifterror, CodeGenOptLevel ol)
: SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()), DAG(dag),
- SL(std::make_unique<SDAGSwitchLowering>(this, funcinfo)), FuncInfo(funcinfo),
- SwiftError(swifterror) {}
+ SL(std::make_unique<SDAGSwitchLowering>(this, funcinfo)),
+ FuncInfo(funcinfo), SwiftError(swifterror) {}
void init(GCFunctionInfo *gfi, AAResults *AA, AssumptionCache *AC,
const TargetLibraryInfo *li);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 91b9d77..70e78af 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -211,12 +211,12 @@
/// the optimization level on a per-function basis.
class OptLevelChanger {
SelectionDAGISel &IS;
- CodeGenOpt::Level SavedOptLevel;
+ CodeGenOptLevel SavedOptLevel;
bool SavedFastISel;
public:
- OptLevelChanger(SelectionDAGISel &ISel,
- CodeGenOpt::Level NewOptLevel) : IS(ISel) {
+ OptLevelChanger(SelectionDAGISel &ISel, CodeGenOptLevel NewOptLevel)
+ : IS(ISel) {
SavedOptLevel = IS.OptLevel;
SavedFastISel = IS.TM.Options.EnableFastISel;
if (NewOptLevel == SavedOptLevel)
@@ -225,9 +225,9 @@
IS.TM.setOptLevel(NewOptLevel);
LLVM_DEBUG(dbgs() << "\nChanging optimization level for Function "
<< IS.MF->getFunction().getName() << "\n");
- LLVM_DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel << " ; After: -O"
- << NewOptLevel << "\n");
- if (NewOptLevel == CodeGenOpt::None) {
+ LLVM_DEBUG(dbgs() << "\tBefore: -O" << static_cast<int>(SavedOptLevel) << " ; After: -O"
+ << static_cast<int>(NewOptLevel) << "\n");
+ if (NewOptLevel == CodeGenOptLevel::None) {
IS.TM.setFastISel(IS.TM.getO0WantsFastISel());
LLVM_DEBUG(
dbgs() << "\tFastISel is "
@@ -241,8 +241,8 @@
return;
LLVM_DEBUG(dbgs() << "\nRestoring optimization level for Function "
<< IS.MF->getFunction().getName() << "\n");
- LLVM_DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel << " ; After: -O"
- << SavedOptLevel << "\n");
+ LLVM_DEBUG(dbgs() << "\tBefore: -O" << static_cast<int>(IS.OptLevel)
+ << " ; After: -O" << static_cast<int>(SavedOptLevel) << "\n");
IS.OptLevel = SavedOptLevel;
IS.TM.setOptLevel(SavedOptLevel);
IS.TM.setFastISel(SavedFastISel);
@@ -252,8 +252,8 @@
//===--------------------------------------------------------------------===//
/// createDefaultScheduler - This creates an instruction scheduler appropriate
/// for the target.
- ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
- CodeGenOpt::Level OptLevel) {
+ ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
+ CodeGenOptLevel OptLevel) {
const TargetLowering *TLI = IS->TLI;
const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
@@ -262,7 +262,7 @@
return SchedulerCtor(IS, OptLevel);
}
- if (OptLevel == CodeGenOpt::None ||
+ if (OptLevel == CodeGenOptLevel::None ||
(ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||
TLI->getSchedulingPreference() == Sched::Source)
return createSourceListDAGScheduler(IS, OptLevel);
@@ -315,7 +315,7 @@
//===----------------------------------------------------------------------===//
SelectionDAGISel::SelectionDAGISel(char &ID, TargetMachine &tm,
- CodeGenOpt::Level OL)
+ CodeGenOptLevel OL)
: MachineFunctionPass(ID), TM(tm), FuncInfo(new FunctionLoweringInfo()),
SwiftError(new SwiftErrorValueTracking()),
CurDAG(new SelectionDAG(tm, OL)),
@@ -335,23 +335,23 @@
}
void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
- if (OptLevel != CodeGenOpt::None)
- AU.addRequired<AAResultsWrapperPass>();
+ if (OptLevel != CodeGenOptLevel::None)
+ AU.addRequired<AAResultsWrapperPass>();
AU.addRequired<GCModuleInfo>();
AU.addRequired<StackProtector>();
AU.addPreserved<GCModuleInfo>();
AU.addRequired<TargetLibraryInfoWrapperPass>();
AU.addRequired<TargetTransformInfoWrapperPass>();
AU.addRequired<AssumptionCacheTracker>();
- if (UseMBPI && OptLevel != CodeGenOpt::None)
- AU.addRequired<BranchProbabilityInfoWrapperPass>();
+ if (UseMBPI && OptLevel != CodeGenOptLevel::None)
+ AU.addRequired<BranchProbabilityInfoWrapperPass>();
AU.addRequired<ProfileSummaryInfoWrapperPass>();
// AssignmentTrackingAnalysis only runs if assignment tracking is enabled for
// the module.
AU.addRequired<AssignmentTrackingAnalysis>();
AU.addPreserved<AssignmentTrackingAnalysis>();
- if (OptLevel != CodeGenOpt::None)
- LazyBlockFrequencyInfoPass::getLazyBFIAnalysisUsage(AU);
+ if (OptLevel != CodeGenOptLevel::None)
+ LazyBlockFrequencyInfoPass::getLazyBFIAnalysisUsage(AU);
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -403,9 +403,9 @@
// it wants to look at it.
TM.resetTargetOptions(Fn);
// Reset OptLevel to None for optnone functions.
- CodeGenOpt::Level NewOptLevel = OptLevel;
- if (OptLevel != CodeGenOpt::None && skipFunction(Fn))
- NewOptLevel = CodeGenOpt::None;
+ CodeGenOptLevel NewOptLevel = OptLevel;
+ if (OptLevel != CodeGenOptLevel::None && skipFunction(Fn))
+ NewOptLevel = CodeGenOptLevel::None;
OptLevelChanger OLC(*this, NewOptLevel);
TII = MF->getSubtarget().getInstrInfo();
@@ -417,7 +417,7 @@
AC = &getAnalysis<AssumptionCacheTracker>().getAssumptionCache(mf.getFunction());
auto *PSI = &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
BlockFrequencyInfo *BFI = nullptr;
- if (PSI && PSI->hasProfileSummary() && OptLevel != CodeGenOpt::None)
+ if (PSI && PSI->hasProfileSummary() && OptLevel != CodeGenOptLevel::None)
BFI = &getAnalysis<LazyBlockFrequencyInfoPass>().getBFI();
FunctionVarLocs const *FnVarLocs = nullptr;
@@ -438,12 +438,12 @@
// into account). That's unfortunate but OK because it just means we won't
// ask for passes that have been required anyway.
- if (UseMBPI && OptLevel != CodeGenOpt::None)
+ if (UseMBPI && OptLevel != CodeGenOptLevel::None)
FuncInfo->BPI = &getAnalysis<BranchProbabilityInfoWrapperPass>().getBPI();
else
FuncInfo->BPI = nullptr;
- if (OptLevel != CodeGenOpt::None)
+ if (OptLevel != CodeGenOptLevel::None)
AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
else
AA = nullptr;
@@ -456,7 +456,7 @@
// We split CSR if the target supports it for the given function
// and the function has only return exits.
- if (OptLevel != CodeGenOpt::None && TLI->supportSplitCSR(MF)) {
+ if (OptLevel != CodeGenOptLevel::None && TLI->supportSplitCSR(MF)) {
FuncInfo->SplitCSR = true;
// Collect all the return blocks.
@@ -935,7 +935,7 @@
CurDAG->VerifyDAGDivergence();
#endif
- if (OptLevel != CodeGenOpt::None)
+ if (OptLevel != CodeGenOptLevel::None)
ComputeLiveOutVRegInfo();
if (ViewISelDAGs && MatchFilterBB)
@@ -1512,7 +1512,7 @@
// Iterate over all basic blocks in the function.
StackProtector &SP = getAnalysis<StackProtector>();
for (const BasicBlock *LLVMBB : RPOT) {
- if (OptLevel != CodeGenOpt::None) {
+ if (OptLevel != CodeGenOptLevel::None) {
bool AllPredsVisited = true;
for (const BasicBlock *Pred : predecessors(LLVMBB)) {
if (!FuncInfo->VisitedBBs.count(Pred)) {
@@ -2180,16 +2180,18 @@
/// operand node N of U during instruction selection that starts at Root.
bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
SDNode *Root) const {
- if (OptLevel == CodeGenOpt::None) return false;
+ if (OptLevel == CodeGenOptLevel::None)
+ return false;
return N.hasOneUse();
}
/// IsLegalToFold - Returns true if the specific operand node N of
/// U can be folded during instruction selection that starts at Root.
bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
- CodeGenOpt::Level OptLevel,
+ CodeGenOptLevel OptLevel,
bool IgnoreChains) {
- if (OptLevel == CodeGenOpt::None) return false;
+ if (OptLevel == CodeGenOptLevel::None)
+ return false;
// If Root use can somehow reach N through a path that doesn't contain
// U then folding N would create a cycle. e.g. In the following
diff --git a/llvm/lib/CodeGen/SwitchLoweringUtils.cpp b/llvm/lib/CodeGen/SwitchLoweringUtils.cpp
index 36a02d5..b01a8be 100644
--- a/llvm/lib/CodeGen/SwitchLoweringUtils.cpp
+++ b/llvm/lib/CodeGen/SwitchLoweringUtils.cpp
@@ -95,7 +95,7 @@
}
// The algorithm below is not suitable for -O0.
- if (TM->getOptLevel() == CodeGenOpt::None)
+ if (TM->getOptLevel() == CodeGenOptLevel::None)
return;
// Split Clusters into minimum number of dense partitions. The algorithm uses
@@ -278,7 +278,7 @@
#endif
// The algorithm below is not suitable for -O0.
- if (TM->getOptLevel() == CodeGenOpt::None)
+ if (TM->getOptLevel() == CodeGenOptLevel::None)
return;
// If target does not have legal shift left, do not emit bit tests at all.
diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp
index 87ac68c..e6ecbc9 100644
--- a/llvm/lib/CodeGen/TargetPassConfig.cpp
+++ b/llvm/lib/CodeGen/TargetPassConfig.cpp
@@ -631,7 +631,7 @@
setStartStopPasses();
}
-CodeGenOpt::Level TargetPassConfig::getOptLevel() const {
+CodeGenOptLevel TargetPassConfig::getOptLevel() const {
return TM->getOptLevel();
}
@@ -846,7 +846,7 @@
if (!DisableVerify)
addPass(createVerifierPass());
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOptLevel::None) {
// Basic AliasAnalysis support.
// Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
// BasicAliasAnalysis wins if they disagree. This is intended to help
@@ -889,13 +889,13 @@
addPass(createUnreachableBlockEliminationPass());
// Prepare expensive constants for SelectionDAG.
- if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting)
+ if (getOptLevel() != CodeGenOptLevel::None && !DisableConstantHoisting)
addPass(createConstantHoistingPass());
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOptLevel::None)
addPass(createReplaceWithVeclibLegacyPass());
- if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining)
+ if (getOptLevel() != CodeGenOptLevel::None && !DisablePartialLibcallInlining)
addPass(createPartiallyInlineLibCallsPass());
// Expand vector predication intrinsics into standard IR instructions.
@@ -913,11 +913,11 @@
if (!DisableExpandReductions)
addPass(createExpandReductionsPass());
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOptLevel::None)
addPass(createTLSVariableHoistPass());
// Convert conditional moves to conditional jumps when profitable.
- if (getOptLevel() != CodeGenOpt::None && !DisableSelectOptimize)
+ if (getOptLevel() != CodeGenOptLevel::None && !DisableSelectOptimize)
addPass(createSelectOptimizePass());
}
@@ -968,7 +968,7 @@
/// Add pass to prepare the LLVM IR for code generation. This should be done
/// before exception handling preparation passes.
void TargetPassConfig::addCodeGenPrepare() {
- if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
+ if (getOptLevel() != CodeGenOptLevel::None && !DisableCGP)
addPass(createCodeGenPreparePass());
}
@@ -1012,7 +1012,8 @@
(TM->Options.EnableGlobalISel &&
EnableGlobalISelOption != cl::BOU_FALSE))
Selector = SelectorType::GlobalISel;
- else if (TM->getOptLevel() == CodeGenOpt::None && TM->getO0WantsFastISel())
+ else if (TM->getOptLevel() == CodeGenOptLevel::None &&
+ TM->getO0WantsFastISel())
Selector = SelectorType::FastISel;
else
Selector = SelectorType::SelectionDAG;
@@ -1129,7 +1130,7 @@
AddingMachinePasses = true;
// Add passes that optimize machine instructions in SSA form.
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOptLevel::None) {
addMachineSSAOptimization();
} else {
// If the target requests it, assign local variables to stack slots relative
@@ -1175,7 +1176,7 @@
addPass(&FixupStatepointCallerSavedID);
// Insert prolog/epilog code. Eliminate abstract frame index references...
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOptLevel::None) {
addPass(&PostRAMachineSinkingID);
addPass(&ShrinkWrapID);
}
@@ -1186,8 +1187,8 @@
addPass(createPrologEpilogInserterPass());
/// Add passes that optimize machine instructions after register allocation.
- if (getOptLevel() != CodeGenOpt::None)
- addMachineLateOptimization();
+ if (getOptLevel() != CodeGenOptLevel::None)
+ addMachineLateOptimization();
// Expand pseudo instructions before second scheduling pass.
addPass(&ExpandPostRAPseudosID);
@@ -1201,7 +1202,7 @@
// Second pass scheduler.
// Let Target optionally insert this pass by itself at some other
// point.
- if (getOptLevel() != CodeGenOpt::None &&
+ if (getOptLevel() != CodeGenOptLevel::None &&
!TM->targetSchedulesPostRAScheduling()) {
if (MISchedPostRA)
addPass(&PostMachineSchedulerID);
@@ -1216,7 +1217,7 @@
}
// Basic block placement.
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOptLevel::None)
addBlockPlacement();
// Insert before XRay Instrumentation.
@@ -1240,7 +1241,8 @@
addPass(&LiveDebugValuesID);
addPass(&MachineSanitizerBinaryMetadataID);
- if (TM->Options.EnableMachineOutliner && getOptLevel() != CodeGenOpt::None &&
+ if (TM->Options.EnableMachineOutliner &&
+ getOptLevel() != CodeGenOptLevel::None &&
EnableMachineOutliner != RunOutliner::NeverOutline) {
bool RunOnAllFunctions =
(EnableMachineOutliner == RunOutliner::AlwaysOutline);
@@ -1344,7 +1346,8 @@
bool TargetPassConfig::getOptimizeRegAlloc() const {
switch (OptimizeRegAlloc) {
- case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
+ case cl::BOU_UNSET:
+ return getOptLevel() != CodeGenOptLevel::None;
case cl::BOU_TRUE: return true;
case cl::BOU_FALSE: return false;
}
diff --git a/llvm/lib/CodeGen/TargetSubtargetInfo.cpp b/llvm/lib/CodeGen/TargetSubtargetInfo.cpp
index ba2c8dd..6c97bc0 100644
--- a/llvm/lib/CodeGen/TargetSubtargetInfo.cpp
+++ b/llvm/lib/CodeGen/TargetSubtargetInfo.cpp
@@ -41,7 +41,7 @@
}
bool TargetSubtargetInfo::enableRALocalReassignment(
- CodeGenOpt::Level OptLevel) const {
+ CodeGenOptLevel OptLevel) const {
return true;
}
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index 45f6126..79fe7f4 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -95,7 +95,7 @@
LiveVariables *LV = nullptr;
LiveIntervals *LIS = nullptr;
AliasAnalysis *AA = nullptr;
- CodeGenOpt::Level OptLevel = CodeGenOpt::None;
+ CodeGenOptLevel OptLevel = CodeGenOptLevel::None;
// The current basic block being processed.
MachineBasicBlock *MBB = nullptr;
@@ -551,7 +551,7 @@
Register RegC,
MachineInstr *MI,
unsigned Dist) {
- if (OptLevel == CodeGenOpt::None)
+ if (OptLevel == CodeGenOptLevel::None)
return false;
// Determine if it's profitable to commute this two address instruction. In
@@ -1231,7 +1231,7 @@
MachineBasicBlock::iterator &nmi,
unsigned SrcIdx, unsigned DstIdx,
unsigned &Dist, bool shouldOnlyCommute) {
- if (OptLevel == CodeGenOpt::None)
+ if (OptLevel == CodeGenOptLevel::None)
return false;
MachineInstr &MI = *mi;
@@ -1757,7 +1757,7 @@
// Disable optimizations if requested. We cannot skip the whole pass as some
// fixups are necessary for correctness.
if (skipFunction(Func.getFunction()))
- OptLevel = CodeGenOpt::None;
+ OptLevel = CodeGenOptLevel::None;
bool MadeChange = false;
diff --git a/llvm/lib/ExecutionEngine/ExecutionEngine.cpp b/llvm/lib/ExecutionEngine/ExecutionEngine.cpp
index 98d7dcb..9e81cca 100644
--- a/llvm/lib/ExecutionEngine/ExecutionEngine.cpp
+++ b/llvm/lib/ExecutionEngine/ExecutionEngine.cpp
@@ -471,7 +471,7 @@
EngineBuilder::EngineBuilder(std::unique_ptr<Module> M)
: M(std::move(M)), WhichEngine(EngineKind::Either), ErrorStr(nullptr),
- OptLevel(CodeGenOpt::Default), MemMgr(nullptr), Resolver(nullptr) {
+ OptLevel(CodeGenOptLevel::Default), MemMgr(nullptr), Resolver(nullptr) {
// IR module verification is enabled by default in debug builds, and disabled
// by default in release builds.
#ifndef NDEBUG
diff --git a/llvm/lib/ExecutionEngine/ExecutionEngineBindings.cpp b/llvm/lib/ExecutionEngine/ExecutionEngineBindings.cpp
index dc9a07e..772a3fa 100644
--- a/llvm/lib/ExecutionEngine/ExecutionEngineBindings.cpp
+++ b/llvm/lib/ExecutionEngine/ExecutionEngineBindings.cpp
@@ -138,8 +138,8 @@
std::string Error;
EngineBuilder builder(std::unique_ptr<Module>(unwrap(M)));
builder.setEngineKind(EngineKind::JIT)
- .setErrorStr(&Error)
- .setOptLevel((CodeGenOpt::Level)OptLevel);
+ .setErrorStr(&Error)
+ .setOptLevel((CodeGenOptLevel)OptLevel);
if (ExecutionEngine *JIT = builder.create()) {
*OutJIT = wrap(JIT);
return 0;
@@ -196,9 +196,9 @@
std::string Error;
EngineBuilder builder(std::move(Mod));
builder.setEngineKind(EngineKind::JIT)
- .setErrorStr(&Error)
- .setOptLevel((CodeGenOpt::Level)options.OptLevel)
- .setTargetOptions(targetOptions);
+ .setErrorStr(&Error)
+ .setOptLevel((CodeGenOptLevel)options.OptLevel)
+ .setTargetOptions(targetOptions);
bool JIT;
if (std::optional<CodeModel::Model> CM = unwrap(options.CodeModel, JIT))
builder.setCodeModel(*CM);
diff --git a/llvm/lib/ExecutionEngine/Orc/JITTargetMachineBuilder.cpp b/llvm/lib/ExecutionEngine/Orc/JITTargetMachineBuilder.cpp
index b66f52f..17a96de 100644
--- a/llvm/lib/ExecutionEngine/Orc/JITTargetMachineBuilder.cpp
+++ b/llvm/lib/ExecutionEngine/Orc/JITTargetMachineBuilder.cpp
@@ -126,16 +126,16 @@
OS << "\n"
<< Indent << " Optimization Level = ";
switch (JTMB.OptLevel) {
- case CodeGenOpt::None:
+ case CodeGenOptLevel::None:
OS << "None";
break;
- case CodeGenOpt::Less:
+ case CodeGenOptLevel::Less:
OS << "Less";
break;
- case CodeGenOpt::Default:
+ case CodeGenOptLevel::Default:
OS << "Default";
break;
- case CodeGenOpt::Aggressive:
+ case CodeGenOptLevel::Aggressive:
OS << "Aggressive";
break;
}
diff --git a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
index 9341c52..8e9200a 100644
--- a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+++ b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
@@ -3394,7 +3394,7 @@
/// "target-features" that determine the TargetMachine are per-function and can
/// be overrided using __attribute__((target("OPTIONS"))).
static std::unique_ptr<TargetMachine>
-createTargetMachine(Function *F, CodeGenOpt::Level OptLevel) {
+createTargetMachine(Function *F, CodeGenOptLevel OptLevel) {
Module *M = F->getParent();
StringRef CPU = F->getFnAttribute("target-cpu").getValueAsString();
@@ -3420,7 +3420,7 @@
// Assume the user requests the most aggressive unrolling, even if the rest of
// the code is optimized using a lower setting.
- CodeGenOpt::Level OptLevel = CodeGenOpt::Aggressive;
+ CodeGenOptLevel OptLevel = CodeGenOptLevel::Aggressive;
std::unique_ptr<TargetMachine> TM = createTargetMachine(F, OptLevel);
FunctionAnalysisManager FAM;
@@ -3453,7 +3453,7 @@
TargetTransformInfo::UnrollingPreferences UP =
gatherUnrollingPreferences(L, SE, TTI,
/*BlockFrequencyInfo=*/nullptr,
- /*ProfileSummaryInfo=*/nullptr, ORE, OptLevel,
+ /*ProfileSummaryInfo=*/nullptr, ORE, static_cast<int>(OptLevel),
/*UserThreshold=*/std::nullopt,
/*UserCount=*/std::nullopt,
/*UserAllowPartial=*/true,
diff --git a/llvm/lib/LTO/LTO.cpp b/llvm/lib/LTO/LTO.cpp
index 2a3f44d..3e008ed 100644
--- a/llvm/lib/LTO/LTO.cpp
+++ b/llvm/lib/LTO/LTO.cpp
@@ -142,8 +142,8 @@
AddUnsigned(-1);
for (const auto &S : Conf.MllvmArgs)
AddString(S);
- AddUnsigned(Conf.CGOptLevel);
- AddUnsigned(Conf.CGFileType);
+ AddUnsigned(static_cast<int>(Conf.CGOptLevel));
+ AddUnsigned(static_cast<int>(Conf.CGFileType));
AddUnsigned(Conf.OptLevel);
AddUnsigned(Conf.Freestanding);
AddString(Conf.OptPipeline);
diff --git a/llvm/lib/LTO/LTOCodeGenerator.cpp b/llvm/lib/LTO/LTOCodeGenerator.cpp
index 1402da7..52a4a9b 100644
--- a/llvm/lib/LTO/LTOCodeGenerator.cpp
+++ b/llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -200,7 +200,7 @@
Config.OptLevel = Level;
Config.PTO.LoopVectorization = Config.OptLevel > 1;
Config.PTO.SLPVectorization = Config.OptLevel > 1;
- std::optional<CodeGenOpt::Level> CGOptLevelOrNone =
+ std::optional<CodeGenOptLevel> CGOptLevelOrNone =
CodeGenOpt::getLevel(Config.OptLevel);
assert(CGOptLevelOrNone && "Unknown optimization level!");
Config.CGOptLevel = *CGOptLevelOrNone;
@@ -306,7 +306,7 @@
bool LTOCodeGenerator::compileOptimizedToFile(const char **Name) {
if (useAIXSystemAssembler())
- setFileType(CGFT_AssemblyFile);
+ setFileType(CodeGenFileType::AssemblyFile);
// make unique temp output file to put generated code
SmallString<128> Filename;
@@ -314,7 +314,8 @@
auto AddStream =
[&](size_t Task,
const Twine &ModuleName) -> std::unique_ptr<CachedFileStream> {
- StringRef Extension(Config.CGFileType == CGFT_AssemblyFile ? "s" : "o");
+ StringRef Extension(
+ Config.CGFileType == CodeGenFileType::AssemblyFile ? "s" : "o");
int FD;
std::error_code EC =
diff --git a/llvm/lib/LTO/ThinLTOCodeGenerator.cpp b/llvm/lib/LTO/ThinLTOCodeGenerator.cpp
index f207b27..02a4535 100644
--- a/llvm/lib/LTO/ThinLTOCodeGenerator.cpp
+++ b/llvm/lib/LTO/ThinLTOCodeGenerator.cpp
@@ -338,7 +338,7 @@
PM.add(createObjCARCContractPass());
// Setup the codegen now.
- if (TM.addPassesToEmitFile(PM, OS, nullptr, CGFT_ObjectFile,
+ if (TM.addPassesToEmitFile(PM, OS, nullptr, CodeGenFileType::ObjectFile,
/* DisableVerify */ true))
report_fatal_error("Failed to setup codegen");
diff --git a/llvm/lib/Target/AArch64/AArch64.h b/llvm/lib/Target/AArch64/AArch64.h
index 76f5566..1a86fc4 100644
--- a/llvm/lib/Target/AArch64/AArch64.h
+++ b/llvm/lib/Target/AArch64/AArch64.h
@@ -36,7 +36,7 @@
FunctionPass *createAArch64ConditionalCompares();
FunctionPass *createAArch64AdvSIMDScalar();
FunctionPass *createAArch64ISelDag(AArch64TargetMachine &TM,
- CodeGenOpt::Level OptLevel);
+ CodeGenOptLevel OptLevel);
FunctionPass *createAArch64StorePairSuppressPass();
FunctionPass *createAArch64ExpandPseudoPass();
FunctionPass *createAArch64SLSHardeningPass();
diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp
index b2c4693..ce1c1f7 100644
--- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp
@@ -5034,7 +5034,7 @@
}
bool AArch64FastISel::selectAtomicCmpXchg(const AtomicCmpXchgInst *I) {
- assert(TM.getOptLevel() == CodeGenOpt::None &&
+ assert(TM.getOptLevel() == CodeGenOptLevel::None &&
"cmpxchg survived AtomicExpand at optlevel > -O0");
auto *RetPairTy = cast<StructType>(I->getType());
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 16ab662..38759a2 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -49,7 +49,7 @@
AArch64DAGToDAGISel() = delete;
explicit AArch64DAGToDAGISel(AArch64TargetMachine &tm,
- CodeGenOpt::Level OptLevel)
+ CodeGenOptLevel OptLevel)
: SelectionDAGISel(ID, tm, OptLevel), Subtarget(nullptr) {}
bool runOnMachineFunction(MachineFunction &MF) override {
@@ -6604,7 +6604,7 @@
/// createAArch64ISelDag - This pass converts a legalized DAG into a
/// AArch64-specific DAG, ready for instruction scheduling.
FunctionPass *llvm::createAArch64ISelDag(AArch64TargetMachine &TM,
- CodeGenOpt::Level OptLevel) {
+ CodeGenOptLevel OptLevel) {
return new AArch64DAGToDAGISel(TM, OptLevel);
}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 5da41ec..30a66c7 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -15707,8 +15707,8 @@
}
bool AArch64TargetLowering::generateFMAsInMachineCombiner(
- EVT VT, CodeGenOpt::Level OptLevel) const {
- return (OptLevel >= CodeGenOpt::Aggressive) && !VT.isScalableVector() &&
+ EVT VT, CodeGenOptLevel OptLevel) const {
+ return (OptLevel >= CodeGenOptLevel::Aggressive) && !VT.isScalableVector() &&
!useSVEForFixedLengthVectorVT(VT);
}
@@ -24427,7 +24427,7 @@
// stack and close enough to the spill slot, this can lead to a situation
// where the monitor always gets cleared and the atomic operation can never
// succeed. So at -O0 lower this operation to a CAS loop.
- if (getTargetMachine().getOptLevel() == CodeGenOpt::None)
+ if (getTargetMachine().getOptLevel() == CodeGenOptLevel::None)
return AtomicExpansionKind::CmpXChg;
// Using CAS for an atomic load has a better chance of succeeding under high
@@ -24479,7 +24479,7 @@
// where the monitor always gets cleared and the atomic operation can never
// succeed. So at -O0 lower this operation to a CAS loop. Also worthwhile if
// we have a single CAS instruction that can replace the loop.
- if (getTargetMachine().getOptLevel() == CodeGenOpt::None ||
+ if (getTargetMachine().getOptLevel() == CodeGenOptLevel::None ||
Subtarget->hasLSE())
return AtomicExpansionKind::CmpXChg;
@@ -24497,7 +24497,7 @@
// on the stack and close enough to the spill slot, this can lead to a
// situation where the monitor always gets cleared and the atomic operation
// can never succeed. So at -O0 we need a late-expanded pseudo-inst instead.
- if (getTargetMachine().getOptLevel() == CodeGenOpt::None)
+ if (getTargetMachine().getOptLevel() == CodeGenOptLevel::None)
return AtomicExpansionKind::None;
// 128-bit atomic cmpxchg is weird; AtomicExpand doesn't know how to expand
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index f2696b6..48b5bc1 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -681,7 +681,7 @@
bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override;
bool generateFMAsInMachineCombiner(EVT VT,
- CodeGenOpt::Level OptLevel) const override;
+ CodeGenOptLevel OptLevel) const override;
const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
ArrayRef<MCPhysReg> getRoundingControlRegisters() const override;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 3a18f37..5ad2e48 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -8533,8 +8533,8 @@
}
unsigned int
-AArch64InstrInfo::getTailDuplicateSize(CodeGenOpt::Level OptLevel) const {
- return OptLevel >= CodeGenOpt::Aggressive ? 6 : 2;
+AArch64InstrInfo::getTailDuplicateSize(CodeGenOptLevel OptLevel) const {
+ return OptLevel >= CodeGenOptLevel::Aggressive ? 6 : 2;
}
unsigned llvm::getBLRCallOpcode(const MachineFunction &MF) {
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index 24ff676..2cd028d 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -343,7 +343,7 @@
std::optional<ParamLoadedValue>
describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
- unsigned int getTailDuplicateSize(CodeGenOpt::Level OptLevel) const override;
+ unsigned int getTailDuplicateSize(CodeGenOptLevel OptLevel) const override;
bool isExtendLikelyToBeFolded(MachineInstr &ExtMI,
MachineRegisterInfo &MRI) const override;
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index 6f7fccd..a3aa4a5 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -320,7 +320,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT,
+ CodeGenOptLevel OL, bool JIT,
bool LittleEndian)
: LLVMTargetMachine(T,
computeDataLayout(TT, Options.MCOptions, LittleEndian),
@@ -358,7 +358,7 @@
// Enable GlobalISel at or below EnableGlobalISelAt0, unless this is
// MachO/CodeModel::Large, which GlobalISel does not support.
- if (getOptLevel() <= EnableGlobalISelAtO &&
+ if (static_cast<int>(getOptLevel()) <= EnableGlobalISelAtO &&
TT.getArch() != Triple::aarch64_32 &&
TT.getEnvironment() != Triple::GNUILP32 &&
!(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO())) {
@@ -451,7 +451,7 @@
AArch64leTargetMachine::AArch64leTargetMachine(
const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
const TargetOptions &Options, std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, bool JIT)
: AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
void AArch64beTargetMachine::anchor() { }
@@ -459,7 +459,7 @@
AArch64beTargetMachine::AArch64beTargetMachine(
const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
const TargetOptions &Options, std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, bool JIT)
: AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
namespace {
@@ -469,7 +469,7 @@
public:
AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
: TargetPassConfig(TM, PM) {
- if (TM.getOptLevel() != CodeGenOpt::None)
+ if (TM.getOptLevel() != CodeGenOptLevel::None)
substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
}
@@ -547,13 +547,14 @@
addPass(createAtomicExpandPass());
// Expand any SVE vector library calls that we can't code generate directly.
- if (EnableSVEIntrinsicOpts && TM->getOptLevel() == CodeGenOpt::Aggressive)
+ if (EnableSVEIntrinsicOpts &&
+ TM->getOptLevel() == CodeGenOptLevel::Aggressive)
addPass(createSVEIntrinsicOptsPass());
// Cmpxchg instructions are often used with a subsequent comparison to
// determine whether it succeeded. We can exploit existing control-flow in
// ldrex/strex loops to simplify this, but it needs tidying up.
- if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
+ if (TM->getOptLevel() != CodeGenOptLevel::None && EnableAtomicTidy)
addPass(createCFGSimplificationPass(SimplifyCFGOptions()
.forwardSwitchCondToPhi(true)
.convertSwitchRangeToICmp(true)
@@ -566,14 +567,14 @@
//
// Run this before LSR to remove the multiplies involved in computing the
// pointer values N iterations ahead.
- if (TM->getOptLevel() != CodeGenOpt::None) {
+ if (TM->getOptLevel() != CodeGenOptLevel::None) {
if (EnableLoopDataPrefetch)
addPass(createLoopDataPrefetchPass());
if (EnableFalkorHWPFFix)
addPass(createFalkorMarkStridedAccessesPass());
}
- if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
+ if (TM->getOptLevel() == CodeGenOptLevel::Aggressive && EnableGEPOpt) {
// Call SeparateConstOffsetFromGEP pass to extract constants within indices
// and lower a GEP with multiple indices to either arithmetic operations or
// multiple GEPs with single index.
@@ -588,19 +589,19 @@
TargetPassConfig::addIRPasses();
- if (getOptLevel() == CodeGenOpt::Aggressive && EnableSelectOpt)
+ if (getOptLevel() == CodeGenOptLevel::Aggressive && EnableSelectOpt)
addPass(createSelectOptimizePass());
addPass(createAArch64GlobalsTaggingPass());
addPass(createAArch64StackTaggingPass(
- /*IsOptNone=*/TM->getOptLevel() == CodeGenOpt::None));
+ /*IsOptNone=*/TM->getOptLevel() == CodeGenOptLevel::None));
// Match complex arithmetic patterns
- if (TM->getOptLevel() >= CodeGenOpt::Default)
+ if (TM->getOptLevel() >= CodeGenOptLevel::Default)
addPass(createComplexDeinterleavingPass(TM));
// Match interleaved memory accesses to ldN/stN intrinsics.
- if (TM->getOptLevel() != CodeGenOpt::None) {
+ if (TM->getOptLevel() != CodeGenOptLevel::None) {
addPass(createInterleavedLoadCombinePass());
addPass(createInterleavedAccessPass());
}
@@ -622,16 +623,17 @@
bool AArch64PassConfig::addPreISel() {
// Run promote constant before global merge, so that the promoted constants
// get a chance to be merged
- if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
+ if (TM->getOptLevel() != CodeGenOptLevel::None && EnablePromoteConstant)
addPass(createAArch64PromoteConstantPass());
// FIXME: On AArch64, this depends on the type.
// Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
// and the offset has to be a multiple of the related size in bytes.
- if ((TM->getOptLevel() != CodeGenOpt::None &&
+ if ((TM->getOptLevel() != CodeGenOptLevel::None &&
EnableGlobalMerge == cl::BOU_UNSET) ||
EnableGlobalMerge == cl::BOU_TRUE) {
- bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
- (EnableGlobalMerge == cl::BOU_UNSET);
+ bool OnlyOptimizeForSize =
+ (TM->getOptLevel() < CodeGenOptLevel::Aggressive) &&
+ (EnableGlobalMerge == cl::BOU_UNSET);
// Merging of extern globals is enabled by default on non-Mach-O as we
// expect it to be generally either beneficial or harmless. On Mach-O it
@@ -652,7 +654,7 @@
}
void AArch64PassConfig::addCodeGenPrepare() {
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOptLevel::None)
addPass(createTypePromotionLegacyPass());
TargetPassConfig::addCodeGenPrepare();
}
@@ -663,7 +665,7 @@
// For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
// references to _TLS_MODULE_BASE_ as possible.
if (TM->getTargetTriple().isOSBinFormatELF() &&
- getOptLevel() != CodeGenOpt::None)
+ getOptLevel() != CodeGenOptLevel::None)
addPass(createAArch64CleanupLocalDynamicTLSPass());
return false;
@@ -675,7 +677,7 @@
}
void AArch64PassConfig::addPreLegalizeMachineIR() {
- if (getOptLevel() == CodeGenOpt::None) {
+ if (getOptLevel() == CodeGenOptLevel::None) {
addPass(createAArch64O0PreLegalizerCombiner());
addPass(new Localizer());
} else {
@@ -692,7 +694,7 @@
}
void AArch64PassConfig::addPreRegBankSelect() {
- bool IsOptNone = getOptLevel() == CodeGenOpt::None;
+ bool IsOptNone = getOptLevel() == CodeGenOptLevel::None;
if (!IsOptNone) {
addPass(createAArch64PostLegalizerCombiner(IsOptNone));
if (EnableGISelLoadStoreOptPostLegal)
@@ -708,7 +710,7 @@
bool AArch64PassConfig::addGlobalInstructionSelect() {
addPass(new InstructionSelect(getOptLevel()));
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOptLevel::None)
addPass(createAArch64PostSelectOptimize());
return false;
}
@@ -717,7 +719,7 @@
// Run default MachineSSAOptimization first.
TargetPassConfig::addMachineSSAOptimization();
- if (TM->getOptLevel() != CodeGenOpt::None)
+ if (TM->getOptLevel() != CodeGenOptLevel::None)
addPass(createAArch64MIPeepholeOptPass());
}
@@ -735,18 +737,19 @@
if (EnableStPairSuppress)
addPass(createAArch64StorePairSuppressPass());
addPass(createAArch64SIMDInstrOptPass());
- if (TM->getOptLevel() != CodeGenOpt::None)
+ if (TM->getOptLevel() != CodeGenOptLevel::None)
addPass(createAArch64StackTaggingPreRAPass());
return true;
}
void AArch64PassConfig::addPreRegAlloc() {
// Change dead register definitions to refer to the zero register.
- if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
+ if (TM->getOptLevel() != CodeGenOptLevel::None &&
+ EnableDeadRegisterElimination)
addPass(createAArch64DeadRegisterDefinitions());
// Use AdvSIMD scalar instructions whenever profitable.
- if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
+ if (TM->getOptLevel() != CodeGenOptLevel::None && EnableAdvSIMDScalar) {
addPass(createAArch64AdvSIMDScalar());
// The AdvSIMD pass may produce copies that can be rewritten to
// be register coalescer friendly.
@@ -756,10 +759,11 @@
void AArch64PassConfig::addPostRegAlloc() {
// Remove redundant copy instructions.
- if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
+ if (TM->getOptLevel() != CodeGenOptLevel::None &&
+ EnableRedundantCopyElimination)
addPass(createAArch64RedundantCopyEliminationPass());
- if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
+ if (TM->getOptLevel() != CodeGenOptLevel::None && usingDefaultRegAlloc())
// Improve performance for some FP/SIMD code for A57.
addPass(createAArch64A57FPLoadBalancing());
}
@@ -771,7 +775,7 @@
// Expand some pseudo instructions to allow proper scheduling.
addPass(createAArch64ExpandPseudoPass());
// Use load/store pair instructions when possible.
- if (TM->getOptLevel() != CodeGenOpt::None) {
+ if (TM->getOptLevel() != CodeGenOptLevel::None) {
if (EnableLoadStoreOpt)
addPass(createAArch64LoadStoreOptimizationPass());
}
@@ -788,7 +792,7 @@
addPass(createAArch64IndirectThunks());
addPass(createAArch64SLSHardeningPass());
- if (TM->getOptLevel() != CodeGenOpt::None) {
+ if (TM->getOptLevel() != CodeGenOptLevel::None) {
if (EnableFalkorHWPFFix)
addPass(createFalkorHWPFFixPass());
}
@@ -798,10 +802,10 @@
// Machine Block Placement might have created new opportunities when run
// at O3, where the Tail Duplication Threshold is set to 4 instructions.
// Run the load/store optimizer once more.
- if (TM->getOptLevel() >= CodeGenOpt::Aggressive && EnableLoadStoreOpt)
+ if (TM->getOptLevel() >= CodeGenOptLevel::Aggressive && EnableLoadStoreOpt)
addPass(createAArch64LoadStoreOptimizationPass());
- if (TM->getOptLevel() >= CodeGenOpt::Aggressive &&
+ if (TM->getOptLevel() >= CodeGenOptLevel::Aggressive &&
EnableAArch64CopyPropagation)
addPass(createMachineCopyPropagationPass(true));
@@ -817,7 +821,7 @@
addPass(createEHContGuardCatchretPass());
}
- if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
+ if (TM->getOptLevel() != CodeGenOptLevel::None && EnableCollectLOH &&
TM->getTargetTriple().isOSBinFormatMachO())
addPass(createAArch64CollectLOHPass());
}
@@ -828,7 +832,7 @@
if (BranchRelaxation)
addPass(&BranchRelaxationPassID);
- if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables)
+ if (TM->getOptLevel() != CodeGenOptLevel::None && EnableCompressJumpTables)
addPass(createAArch64CompressJumpTablesPass());
}
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.h b/llvm/lib/Target/AArch64/AArch64TargetMachine.h
index e9b5f48..12b9718 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.h
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.h
@@ -30,7 +30,7 @@
AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT, bool IsLittleEndian);
~AArch64TargetMachine() override;
@@ -80,8 +80,8 @@
AArch64leTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT);
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
+ bool JIT);
};
// AArch64 big endian target machine.
@@ -93,8 +93,8 @@
AArch64beTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT);
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
+ bool JIT);
};
} // end namespace llvm
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
index 5e248f56..09636bf 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
@@ -434,7 +434,7 @@
auto *TPC = &getAnalysis<TargetPassConfig>();
const Function &F = MF.getFunction();
bool EnableOpt =
- MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
+ MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !skipFunction(F);
const AArch64Subtarget &ST = MF.getSubtarget<AArch64Subtarget>();
const auto *LI = ST.getLegalizerInfo();
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
index cf13161..d9678be 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
@@ -479,7 +479,7 @@
const Function &F = MF.getFunction();
bool EnableOpt =
- MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
+ MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !skipFunction(F);
GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
MachineDominatorTree *MDT = &getAnalysis<MachineDominatorTree>();
CombinerInfo CInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 3d00df5..b7101f4 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -215,8 +215,7 @@
};
Pass *createAMDGPUStructurizeCFGPass();
-FunctionPass *createAMDGPUISelDag(TargetMachine &TM,
- CodeGenOpt::Level OptLevel);
+FunctionPass *createAMDGPUISelDag(TargetMachine &TM, CodeGenOptLevel OptLevel);
ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
struct AMDGPUAlwaysInlinePass : PassInfoMixin<AMDGPUAlwaysInlinePass> {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 5c11549..05deb69 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -112,12 +112,12 @@
/// This pass converts a legalized DAG into a AMDGPU-specific
// DAG, ready for instruction scheduling.
FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM,
- CodeGenOpt::Level OptLevel) {
+ CodeGenOptLevel OptLevel) {
return new AMDGPUDAGToDAGISel(TM, OptLevel);
}
AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM,
- CodeGenOpt::Level OptLevel)
+ CodeGenOptLevel OptLevel)
: SelectionDAGISel(ID, TM, OptLevel) {
EnableLateStructurizeCFG = AMDGPUTargetMachine::EnableLateStructurizeCFG;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
index 06a03cf..7b4a1a4 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
@@ -92,7 +92,7 @@
AMDGPUDAGToDAGISel() = delete;
- explicit AMDGPUDAGToDAGISel(TargetMachine &TM, CodeGenOpt::Level OptLevel);
+ explicit AMDGPUDAGToDAGISel(TargetMachine &TM, CodeGenOptLevel OptLevel);
~AMDGPUDAGToDAGISel() override = default;
void getAnalysisUsage(AnalysisUsage &AU) const override;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 1bde2f3..9f13f58 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -1710,7 +1710,7 @@
}
bool AMDGPUInstructionSelector::selectSBarrier(MachineInstr &MI) const {
- if (TM.getOptLevel() > CodeGenOpt::None) {
+ if (TM.getOptLevel() > CodeGenOptLevel::None) {
unsigned WGSize = STI.getFlatWorkGroupSizes(MF->getFunction()).second;
if (WGSize <= STI.getWavefrontSize()) {
MachineBasicBlock *MBB = MI.getParent();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
index 21cf479..7b18e1f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
@@ -470,7 +470,7 @@
auto *TPC = &getAnalysis<TargetPassConfig>();
const Function &F = MF.getFunction();
bool EnableOpt =
- MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
+ MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !skipFunction(F);
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
const AMDGPULegalizerInfo *LI =
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
index 876aa6d..0c7e198 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
@@ -266,7 +266,7 @@
auto *TPC = &getAnalysis<TargetPassConfig>();
const Function &F = MF.getFunction();
bool EnableOpt =
- MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
+ MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !skipFunction(F);
GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
// Enable CSE.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
index b432d51..20e1aaa 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
@@ -444,7 +444,7 @@
auto *TPC = &getAnalysis<TargetPassConfig>();
const Function &F = MF.getFunction();
bool EnableOpt =
- MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
+ MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !skipFunction(F);
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 074280b..481fbaf 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -546,7 +546,7 @@
TargetOptions Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OptLevel)
+ CodeGenOptLevel OptLevel)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
FS, Options, getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
@@ -827,7 +827,7 @@
TargetOptions Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
: AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
const TargetSubtargetInfo *
@@ -896,7 +896,7 @@
DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
DAG->addMutation(ST.createFillMFMAShadowMutation(DAG->TII));
DAG->addMutation(createIGroupLPDAGMutation());
- if (isPassEnabled(EnableVOPD, CodeGenOpt::Less))
+ if (isPassEnabled(EnableVOPD, CodeGenOptLevel::Less))
DAG->addMutation(createVOPDPairingMutation());
return DAG;
}
@@ -943,7 +943,7 @@
}
void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
- if (getOptLevel() == CodeGenOpt::Aggressive)
+ if (getOptLevel() == CodeGenOptLevel::Aggressive)
addPass(createGVNPass());
else
addPass(createEarlyCSEPass());
@@ -998,22 +998,22 @@
// AMDGPUAttributor infers lack of llvm.amdgcn.lds.kernel.id calls, so run
// after their introduction
- if (TM.getOptLevel() > CodeGenOpt::None)
+ if (TM.getOptLevel() > CodeGenOptLevel::None)
addPass(createAMDGPUAttributorPass());
- if (TM.getOptLevel() > CodeGenOpt::None)
+ if (TM.getOptLevel() > CodeGenOptLevel::None)
addPass(createInferAddressSpacesPass());
// Run atomic optimizer before Atomic Expand
if ((TM.getTargetTriple().getArch() == Triple::amdgcn) &&
- (TM.getOptLevel() >= CodeGenOpt::Less) &&
+ (TM.getOptLevel() >= CodeGenOptLevel::Less) &&
(AMDGPUAtomicOptimizerStrategy != ScanOptions::None)) {
addPass(createAMDGPUAtomicOptimizerPass(AMDGPUAtomicOptimizerStrategy));
}
addPass(createAtomicExpandPass());
- if (TM.getOptLevel() > CodeGenOpt::None) {
+ if (TM.getOptLevel() > CodeGenOptLevel::None) {
addPass(createAMDGPUPromoteAlloca());
if (isPassEnabled(EnableScalarIRPasses))
@@ -1035,7 +1035,7 @@
// Try to hoist loop invariant parts of divisions AMDGPUCodeGenPrepare may
// have expanded.
- if (TM.getOptLevel() > CodeGenOpt::Less)
+ if (TM.getOptLevel() > CodeGenOptLevel::Less)
addPass(createLICMPass());
}
@@ -1081,7 +1081,7 @@
}
bool AMDGPUPassConfig::addPreISel() {
- if (TM->getOptLevel() > CodeGenOpt::None)
+ if (TM->getOptLevel() > CodeGenOptLevel::None)
addPass(createFlattenCFGPass());
return false;
}
@@ -1132,10 +1132,10 @@
bool GCNPassConfig::addPreISel() {
AMDGPUPassConfig::addPreISel();
- if (TM->getOptLevel() > CodeGenOpt::None)
+ if (TM->getOptLevel() > CodeGenOptLevel::None)
addPass(createAMDGPULateCodeGenPreparePass());
- if (TM->getOptLevel() > CodeGenOpt::None)
+ if (TM->getOptLevel() > CodeGenOptLevel::None)
addPass(createSinkingPass());
// Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
@@ -1158,7 +1158,7 @@
}
addPass(createLCSSAPass());
- if (TM->getOptLevel() > CodeGenOpt::Less)
+ if (TM->getOptLevel() > CodeGenOptLevel::Less)
addPass(&AMDGPUPerfHintAnalysisID);
return false;
@@ -1209,7 +1209,7 @@
}
void GCNPassConfig::addPreLegalizeMachineIR() {
- bool IsOptNone = getOptLevel() == CodeGenOpt::None;
+ bool IsOptNone = getOptLevel() == CodeGenOptLevel::None;
addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
addPass(new Localizer());
}
@@ -1220,7 +1220,7 @@
}
void GCNPassConfig::addPreRegBankSelect() {
- bool IsOptNone = getOptLevel() == CodeGenOpt::None;
+ bool IsOptNone = getOptLevel() == CodeGenOptLevel::None;
addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
}
@@ -1230,7 +1230,7 @@
}
void GCNPassConfig::addPreGlobalInstructionSelect() {
- bool IsOptNone = getOptLevel() == CodeGenOpt::None;
+ bool IsOptNone = getOptLevel() == CodeGenOptLevel::None;
addPass(createAMDGPURegBankCombiner(IsOptNone));
}
@@ -1277,7 +1277,7 @@
// This is not an essential optimization and it has a noticeable impact on
// compilation time, so we only enable it from O2.
- if (TM->getOptLevel() > CodeGenOpt::Less)
+ if (TM->getOptLevel() > CodeGenOptLevel::Less)
insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
// FIXME: when an instruction has a Killed operand, and the instruction is
@@ -1385,32 +1385,32 @@
void GCNPassConfig::addPostRegAlloc() {
addPass(&SIFixVGPRCopiesID);
- if (getOptLevel() > CodeGenOpt::None)
+ if (getOptLevel() > CodeGenOptLevel::None)
addPass(&SIOptimizeExecMaskingID);
TargetPassConfig::addPostRegAlloc();
}
void GCNPassConfig::addPreSched2() {
- if (TM->getOptLevel() > CodeGenOpt::None)
+ if (TM->getOptLevel() > CodeGenOptLevel::None)
addPass(createSIShrinkInstructionsPass());
addPass(&SIPostRABundlerID);
}
void GCNPassConfig::addPreEmitPass() {
- if (isPassEnabled(EnableVOPD, CodeGenOpt::Less))
+ if (isPassEnabled(EnableVOPD, CodeGenOptLevel::Less))
addPass(&GCNCreateVOPDID);
addPass(createSIMemoryLegalizerPass());
addPass(createSIInsertWaitcntsPass());
addPass(createSIModeRegisterPass());
- if (getOptLevel() > CodeGenOpt::None)
+ if (getOptLevel() > CodeGenOptLevel::None)
addPass(&SIInsertHardClausesID);
addPass(&SILateBranchLoweringPassID);
- if (isPassEnabled(EnableSetWavePriority, CodeGenOpt::Less))
+ if (isPassEnabled(EnableSetWavePriority, CodeGenOptLevel::Less))
addPass(createAMDGPUSetWavePriorityPass());
- if (getOptLevel() > CodeGenOpt::None)
+ if (getOptLevel() > CodeGenOptLevel::None)
addPass(&SIPreEmitPeepholeID);
// The hazard recognizer that runs as part of the post-ra scheduler does not
// guarantee to be able handle all hazards correctly. This is because if there
@@ -1422,7 +1422,7 @@
// cases.
addPass(&PostRAHazardRecognizerID);
- if (isPassEnabled(EnableInsertDelayAlu, CodeGenOpt::Less))
+ if (isPassEnabled(EnableInsertDelayAlu, CodeGenOptLevel::Less))
addPass(&AMDGPUInsertDelayAluID);
addPass(&BranchRelaxationPassID);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
index 2426be4..9051a61 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
@@ -41,7 +41,7 @@
AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, TargetOptions Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL);
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL);
~AMDGPUTargetMachine() override;
const TargetSubtargetInfo *getSubtargetImpl() const;
@@ -79,7 +79,7 @@
GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, TargetOptions Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
@@ -137,7 +137,7 @@
/// be used given that a pass shall work at an optimization \p Level
/// minimum.
bool isPassEnabled(const cl::opt<bool> &Opt,
- CodeGenOpt::Level Level = CodeGenOpt::Default) const {
+ CodeGenOptLevel Level = CodeGenOptLevel::Default) const {
if (Opt.getNumOccurrences())
return Opt;
if (TM->getOptLevel() < Level)
diff --git a/llvm/lib/Target/AMDGPU/R600.h b/llvm/lib/Target/AMDGPU/R600.h
index 2b0a887..6c40c28 100644
--- a/llvm/lib/Target/AMDGPU/R600.h
+++ b/llvm/lib/Target/AMDGPU/R600.h
@@ -27,7 +27,7 @@
FunctionPass *createR600Packetizer();
FunctionPass *createR600ControlFlowFinalizer();
FunctionPass *createR600MachineCFGStructurizerPass();
-FunctionPass *createR600ISelDag(TargetMachine &TM, CodeGenOpt::Level OptLevel);
+FunctionPass *createR600ISelDag(TargetMachine &TM, CodeGenOptLevel OptLevel);
ModulePass *createR600OpenCLImageTypeLoweringPass();
void initializeR600ClauseMergePassPass(PassRegistry &);
diff --git a/llvm/lib/Target/AMDGPU/R600ISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/R600ISelDAGToDAG.cpp
index 20c2ff8..293db13 100644
--- a/llvm/lib/Target/AMDGPU/R600ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/R600ISelDAGToDAG.cpp
@@ -30,7 +30,7 @@
public:
R600DAGToDAGISel() = delete;
- explicit R600DAGToDAGISel(TargetMachine &TM, CodeGenOpt::Level OptLevel)
+ explicit R600DAGToDAGISel(TargetMachine &TM, CodeGenOptLevel OptLevel)
: AMDGPUDAGToDAGISel(TM, OptLevel) {}
void Select(SDNode *N) override;
@@ -183,6 +183,6 @@
/// This pass converts a legalized DAG into a R600-specific
// DAG, ready for instruction scheduling.
FunctionPass *llvm::createR600ISelDag(TargetMachine &TM,
- CodeGenOpt::Level OptLevel) {
+ CodeGenOptLevel OptLevel) {
return new R600DAGToDAGISel(TM, OptLevel);
}
diff --git a/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp b/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
index 3684058..6cd4fd4 100644
--- a/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
@@ -53,7 +53,7 @@
TargetOptions Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
: AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
setRequiresStructuredCFG(true);
diff --git a/llvm/lib/Target/AMDGPU/R600TargetMachine.h b/llvm/lib/Target/AMDGPU/R600TargetMachine.h
index f0e3cd3..3fe54c7 100644
--- a/llvm/lib/Target/AMDGPU/R600TargetMachine.h
+++ b/llvm/lib/Target/AMDGPU/R600TargetMachine.h
@@ -33,7 +33,7 @@
R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, TargetOptions Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
index db32346..32da233 100644
--- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
@@ -765,7 +765,7 @@
for (auto MI : PHINodes) {
processPHINode(*MI);
}
- if (MF.getTarget().getOptLevel() > CodeGenOpt::None && EnableM0Merge)
+ if (MF.getTarget().getOptLevel() > CodeGenOptLevel::None && EnableM0Merge)
hoistAndMergeSGPRInits(AMDGPU::M0, *MRI, TRI, *MDT, TII);
SiblingPenalty.clear();
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 998904b..3eba40d 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -2346,7 +2346,7 @@
// Everything live out of a block is spilled with fast regalloc, so it's
// almost certain that spilling will be required.
- if (TM.getOptLevel() == CodeGenOpt::None)
+ if (TM.getOptLevel() == CodeGenOptLevel::None)
HasStackObjects = true;
// For now assume stack access is needed in any callee functions, so we need
@@ -8498,7 +8498,7 @@
return SDValue(DAG.getMachineNode(Opc, DL, Op->getVTList(), Ops), 0);
}
case Intrinsic::amdgcn_s_barrier: {
- if (getTargetMachine().getOptLevel() > CodeGenOpt::None) {
+ if (getTargetMachine().getOptLevel() > CodeGenOptLevel::None) {
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
unsigned WGSize = ST.getFlatWorkGroupSizes(MF.getFunction()).second;
if (WGSize <= ST.getWavefrontSize())
@@ -12994,7 +12994,7 @@
SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
- if (getTargetMachine().getOptLevel() == CodeGenOpt::None)
+ if (getTargetMachine().getOptLevel() == CodeGenOptLevel::None)
return SDValue();
switch (N->getOpcode()) {
case ISD::ADD:
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index 122060e..7358ad9 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -1824,7 +1824,7 @@
ForceEmitWaitcnt[T] = false;
OptNone = MF.getFunction().hasOptNone() ||
- MF.getTarget().getOptLevel() == CodeGenOpt::None;
+ MF.getTarget().getOptLevel() == CodeGenOptLevel::None;
HardwareLimits Limits = {};
Limits.VmcntMax = AMDGPU::getVmcntBitMask(IV);
diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
index a173adb..f178324 100644
--- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
@@ -848,8 +848,8 @@
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
TII = ST.getInstrInfo();
TRI = &TII->getRegisterInfo();
- EnableOptimizeEndCf =
- RemoveRedundantEndcf && MF.getTarget().getOptLevel() > CodeGenOpt::None;
+ EnableOptimizeEndCf = RemoveRedundantEndcf &&
+ MF.getTarget().getOptLevel() > CodeGenOptLevel::None;
// This doesn't actually need LiveIntervals, but we can preserve them.
LIS = getAnalysisIfAvailable<LiveIntervals>();
diff --git a/llvm/lib/Target/ARC/ARC.h b/llvm/lib/Target/ARC/ARC.h
index d8ccc47..b81016d 100644
--- a/llvm/lib/Target/ARC/ARC.h
+++ b/llvm/lib/Target/ARC/ARC.h
@@ -23,8 +23,7 @@
class FunctionPass;
class PassRegistry;
-FunctionPass *createARCISelDag(ARCTargetMachine &TM,
- CodeGenOpt::Level OptLevel);
+FunctionPass *createARCISelDag(ARCTargetMachine &TM, CodeGenOptLevel OptLevel);
FunctionPass *createARCExpandPseudosPass();
FunctionPass *createARCOptAddrMode();
FunctionPass *createARCBranchFinalizePass();
diff --git a/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp b/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp
index 2a66cf8..28e35f8 100644
--- a/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp
@@ -45,7 +45,7 @@
ARCDAGToDAGISel() = delete;
- ARCDAGToDAGISel(ARCTargetMachine &TM, CodeGenOpt::Level OptLevel)
+ ARCDAGToDAGISel(ARCTargetMachine &TM, CodeGenOptLevel OptLevel)
: SelectionDAGISel(ID, TM, OptLevel) {}
void Select(SDNode *N) override;
@@ -69,7 +69,7 @@
/// This pass converts a legalized DAG into a ARC-specific DAG, ready for
/// instruction scheduling.
FunctionPass *llvm::createARCISelDag(ARCTargetMachine &TM,
- CodeGenOpt::Level OptLevel) {
+ CodeGenOptLevel OptLevel) {
return new ARCDAGToDAGISel(TM, OptLevel);
}
diff --git a/llvm/lib/Target/ARC/ARCTargetMachine.cpp b/llvm/lib/Target/ARC/ARCTargetMachine.cpp
index 2527d6a..d4ae325 100644
--- a/llvm/lib/Target/ARC/ARCTargetMachine.cpp
+++ b/llvm/lib/Target/ARC/ARCTargetMachine.cpp
@@ -32,7 +32,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(T,
"e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
"f32:32:32-i64:32-f64:32-a:0:32-n32",
diff --git a/llvm/lib/Target/ARC/ARCTargetMachine.h b/llvm/lib/Target/ARC/ARCTargetMachine.h
index 26d9111..0fc4243 100644
--- a/llvm/lib/Target/ARC/ARCTargetMachine.h
+++ b/llvm/lib/Target/ARC/ARCTargetMachine.h
@@ -29,7 +29,7 @@
ARCTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
~ARCTargetMachine() override;
diff --git a/llvm/lib/Target/ARM/ARM.h b/llvm/lib/Target/ARM/ARM.h
index 2013bfd..ecfca65 100644
--- a/llvm/lib/Target/ARM/ARM.h
+++ b/llvm/lib/Target/ARM/ARM.h
@@ -37,7 +37,7 @@
FunctionPass *createARMBlockPlacementPass();
Pass *createARMParallelDSPPass();
FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
- CodeGenOpt::Level OptLevel);
+ CodeGenOptLevel OptLevel);
FunctionPass *createA15SDOptimizerPass();
FunctionPass *createARMLoadStoreOptimizationPass(bool PreAlloc = false);
FunctionPass *createARMExpandPseudoPass();
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index 41dee3e..15cda9b 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -136,13 +136,13 @@
else if (F.hasOptSize())
// For small size, but speed and debugging illusion preserved
OptimizationGoal = 3;
- else if (TM.getOptLevel() == CodeGenOpt::Aggressive)
+ else if (TM.getOptLevel() == CodeGenOptLevel::Aggressive)
// Aggressively for speed, small size and debug illusion sacrificed
OptimizationGoal = 2;
- else if (TM.getOptLevel() > CodeGenOpt::None)
+ else if (TM.getOptLevel() > CodeGenOptLevel::None)
// For speed, but small size and good debug illusion preserved
OptimizationGoal = 1;
- else // TM.getOptLevel() == CodeGenOpt::None
+ else // TM.getOptLevel() == CodeGenOptLevel::None
// For good debugging, but speed and small size preserved
OptimizationGoal = 5;
diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
index a6682f0..7a3ba58 100644
--- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -343,9 +343,9 @@
// Align blocks where the previous block does not fall through. This may add
// extra NOP's but they will not be executed. It uses the PrefLoopAlignment as a
-// measure of how much to align, and only runs at CodeGenOpt::Aggressive.
+// measure of how much to align, and only runs at CodeGenOptLevel::Aggressive.
static bool AlignBlocks(MachineFunction *MF, const ARMSubtarget *STI) {
- if (MF->getTarget().getOptLevel() != CodeGenOpt::Aggressive ||
+ if (MF->getTarget().getOptLevel() != CodeGenOptLevel::Aggressive ||
MF->getFunction().hasOptSize())
return false;
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index acd2e4b..984d8d3 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -63,7 +63,7 @@
ARMDAGToDAGISel() = delete;
- explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm, CodeGenOpt::Level OptLevel)
+ explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm, CodeGenOptLevel OptLevel)
: SelectionDAGISel(ID, tm, OptLevel) {}
bool runOnMachineFunction(MachineFunction &MF) override {
@@ -499,7 +499,7 @@
/// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at
/// least on current ARM implementations) which should be avoidded.
bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
- if (OptLevel == CodeGenOpt::None)
+ if (OptLevel == CodeGenOptLevel::None)
return true;
if (!Subtarget->hasVMLxHazards())
@@ -5894,6 +5894,6 @@
/// ARM-specific DAG, ready for instruction scheduling.
///
FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
- CodeGenOpt::Level OptLevel) {
+ CodeGenOptLevel OptLevel) {
return new ARMDAGToDAGISel(TM, OptLevel);
}
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 56300bd..d9ae95d 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -1335,7 +1335,7 @@
// On v8, we have particularly efficient implementations of atomic fences
// if they can be combined with nearby atomic loads and stores.
if (!Subtarget->hasAcquireRelease() ||
- getTargetMachine().getOptLevel() == 0) {
+ getTargetMachine().getOptLevel() == CodeGenOptLevel::None) {
// Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
InsertFencesForAtomic = true;
}
@@ -21316,7 +21316,7 @@
// the stack and close enough to the spill slot, this can lead to a
// situation where the monitor always gets cleared and the atomic operation
// can never succeed. So at -O0 lower this operation to a CAS loop.
- if (getTargetMachine().getOptLevel() == CodeGenOpt::None)
+ if (getTargetMachine().getOptLevel() == CodeGenOptLevel::None)
return AtomicExpansionKind::CmpXChg;
return AtomicExpansionKind::LLSC;
}
@@ -21340,8 +21340,8 @@
HasAtomicCmpXchg = Subtarget->hasV7Ops();
else
HasAtomicCmpXchg = Subtarget->hasV6Ops();
- if (getTargetMachine().getOptLevel() != 0 && HasAtomicCmpXchg &&
- Size <= (Subtarget->isMClass() ? 32U : 64U))
+ if (getTargetMachine().getOptLevel() != CodeGenOptLevel::None &&
+ HasAtomicCmpXchg && Size <= (Subtarget->isMClass() ? 32U : 64U))
return AtomicExpansionKind::LLSC;
return AtomicExpansionKind::None;
}
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index 39d8607..a80d485 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -220,7 +220,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool isLittle)
+ CodeGenOptLevel OL, bool isLittle)
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
CPU, FS, Options, getEffectiveRelocModel(TT, RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
@@ -328,7 +328,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
: ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
@@ -336,7 +336,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
: ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
namespace {
@@ -422,7 +422,7 @@
// Cmpxchg instructions are often used with a subsequent comparison to
// determine whether it succeeded. We can exploit existing control-flow in
// ldrex/strex loops to simplify this, but it needs tidying up.
- if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
+ if (TM->getOptLevel() != CodeGenOptLevel::None && EnableAtomicTidy)
addPass(createCFGSimplificationPass(
SimplifyCFGOptions().hoistCommonInsts(true).sinkCommonInsts(true),
[this](const Function &F) {
@@ -436,15 +436,15 @@
TargetPassConfig::addIRPasses();
// Run the parallel DSP pass.
- if (getOptLevel() == CodeGenOpt::Aggressive)
+ if (getOptLevel() == CodeGenOptLevel::Aggressive)
addPass(createARMParallelDSPPass());
// Match complex arithmetic patterns
- if (TM->getOptLevel() >= CodeGenOpt::Default)
+ if (TM->getOptLevel() >= CodeGenOptLevel::Default)
addPass(createComplexDeinterleavingPass(TM));
// Match interleaved memory accesses to ldN/stN intrinsics.
- if (TM->getOptLevel() != CodeGenOpt::None)
+ if (TM->getOptLevel() != CodeGenOptLevel::None)
addPass(createInterleavedAccessPass());
// Add Control Flow Guard checks.
@@ -456,13 +456,13 @@
}
void ARMPassConfig::addCodeGenPrepare() {
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOptLevel::None)
addPass(createTypePromotionLegacyPass());
TargetPassConfig::addCodeGenPrepare();
}
bool ARMPassConfig::addPreISel() {
- if ((TM->getOptLevel() != CodeGenOpt::None &&
+ if ((TM->getOptLevel() != CodeGenOptLevel::None &&
EnableGlobalMerge == cl::BOU_UNSET) ||
EnableGlobalMerge == cl::BOU_TRUE) {
// FIXME: This is using the thumb1 only constant value for
@@ -470,8 +470,9 @@
// to look into using the old value for non-thumb1 code of
// 4095 based on the TargetMachine, but this starts to become
// tricky when doing code gen per function.
- bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
- (EnableGlobalMerge == cl::BOU_UNSET);
+ bool OnlyOptimizeForSize =
+ (TM->getOptLevel() < CodeGenOptLevel::Aggressive) &&
+ (EnableGlobalMerge == cl::BOU_UNSET);
// Merging of extern globals is enabled by default on non-Mach-O as we
// expect it to be generally either beneficial or harmless. On Mach-O it
// is disabled as we emit the .subsections_via_symbols directive which
@@ -481,7 +482,7 @@
MergeExternalByDefault));
}
- if (TM->getOptLevel() != CodeGenOpt::None) {
+ if (TM->getOptLevel() != CodeGenOptLevel::None) {
addPass(createHardwareLoopsLegacyPass());
addPass(createMVETailPredicationPass());
// FIXME: IR passes can delete address-taken basic blocks, deleting
@@ -523,8 +524,8 @@
}
void ARMPassConfig::addPreRegAlloc() {
- if (getOptLevel() != CodeGenOpt::None) {
- if (getOptLevel() == CodeGenOpt::Aggressive)
+ if (getOptLevel() != CodeGenOptLevel::None) {
+ if (getOptLevel() == CodeGenOptLevel::Aggressive)
addPass(&MachinePipelinerID);
addPass(createMVETPAndVPTOptimisationsPass());
@@ -540,7 +541,7 @@
}
void ARMPassConfig::addPreSched2() {
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOptLevel::None) {
if (EnableARMLoadStoreOpt)
addPass(createARMLoadStoreOptimizationPass());
@@ -552,7 +553,7 @@
// proper scheduling.
addPass(createARMExpandPseudoPass());
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOptLevel::None) {
// When optimising for size, always run the Thumb2SizeReduction pass before
// IfConversion. Otherwise, check whether IT blocks are restricted
// (e.g. in v8, IfConversion depends on Thumb instruction widths)
@@ -569,7 +570,7 @@
// Add both scheduling passes to give the subtarget an opportunity to pick
// between them.
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOptLevel::None) {
addPass(&PostMachineSchedulerID);
addPass(&PostRASchedulerID);
}
@@ -588,7 +589,7 @@
}));
// Don't optimize barriers or block placement at -O0.
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOptLevel::None) {
addPass(createARMBlockPlacementPass());
addPass(createARMOptimizeBarriersPass());
}
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.h b/llvm/lib/Target/ARM/ARMTargetMachine.h
index fb04433..1754382 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.h
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.h
@@ -42,7 +42,7 @@
ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool isLittle);
~ARMBaseTargetMachine() override;
@@ -92,7 +92,7 @@
ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
};
@@ -103,7 +103,7 @@
ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
};
diff --git a/llvm/lib/Target/AVR/AVR.h b/llvm/lib/Target/AVR/AVR.h
index 020c3d4..4b1336e 100644
--- a/llvm/lib/Target/AVR/AVR.h
+++ b/llvm/lib/Target/AVR/AVR.h
@@ -26,8 +26,7 @@
class PassRegistry;
Pass *createAVRShiftExpandPass();
-FunctionPass *createAVRISelDag(AVRTargetMachine &TM,
- CodeGenOpt::Level OptLevel);
+FunctionPass *createAVRISelDag(AVRTargetMachine &TM, CodeGenOptLevel OptLevel);
FunctionPass *createAVRExpandPseudoPass();
FunctionPass *createAVRFrameAnalyzerPass();
FunctionPass *createAVRBranchSelectionPass();
diff --git a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
index 214799a..196122e 100644
--- a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
@@ -33,7 +33,7 @@
AVRDAGToDAGISel() = delete;
- AVRDAGToDAGISel(AVRTargetMachine &TM, CodeGenOpt::Level OptLevel)
+ AVRDAGToDAGISel(AVRTargetMachine &TM, CodeGenOptLevel OptLevel)
: SelectionDAGISel(ID, TM, OptLevel), Subtarget(nullptr) {}
bool runOnMachineFunction(MachineFunction &MF) override;
@@ -585,6 +585,6 @@
}
FunctionPass *llvm::createAVRISelDag(AVRTargetMachine &TM,
- CodeGenOpt::Level OptLevel) {
+ CodeGenOptLevel OptLevel) {
return new AVRDAGToDAGISel(TM, OptLevel);
}
diff --git a/llvm/lib/Target/AVR/AVRTargetMachine.cpp b/llvm/lib/Target/AVR/AVRTargetMachine.cpp
index e0c0514..e0776a6 100644
--- a/llvm/lib/Target/AVR/AVRTargetMachine.cpp
+++ b/llvm/lib/Target/AVR/AVRTargetMachine.cpp
@@ -48,7 +48,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(T, AVRDataLayout, TT, getCPU(CPU), FS, Options,
getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
diff --git a/llvm/lib/Target/AVR/AVRTargetMachine.h b/llvm/lib/Target/AVR/AVRTargetMachine.h
index 0fee27d..c19df2b 100644
--- a/llvm/lib/Target/AVR/AVRTargetMachine.h
+++ b/llvm/lib/Target/AVR/AVRTargetMachine.h
@@ -32,7 +32,7 @@
AVRTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
const AVRSubtarget *getSubtargetImpl() const;
diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.cpp b/llvm/lib/Target/BPF/BPFTargetMachine.cpp
index 3926885..983a4ff 100644
--- a/llvm/lib/Target/BPF/BPFTargetMachine.cpp
+++ b/llvm/lib/Target/BPF/BPFTargetMachine.cpp
@@ -62,7 +62,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
@@ -159,7 +159,7 @@
void BPFPassConfig::addPreEmitPass() {
addPass(createBPFMIPreEmitCheckingPass());
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOptLevel::None)
if (!DisableMIPeephole)
addPass(createBPFMIPreEmitPeepholePass());
}
diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.h b/llvm/lib/Target/BPF/BPFTargetMachine.h
index 1f22fcc..4e6adc7 100644
--- a/llvm/lib/Target/BPF/BPFTargetMachine.h
+++ b/llvm/lib/Target/BPF/BPFTargetMachine.h
@@ -26,7 +26,7 @@
BPFTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
const BPFSubtarget *getSubtargetImpl() const { return &Subtarget; }
diff --git a/llvm/lib/Target/CSKY/CSKY.h b/llvm/lib/Target/CSKY/CSKY.h
index 871a7d7..7ca630c 100644
--- a/llvm/lib/Target/CSKY/CSKY.h
+++ b/llvm/lib/Target/CSKY/CSKY.h
@@ -23,7 +23,7 @@
class PassRegistry;
FunctionPass *createCSKYISelDag(CSKYTargetMachine &TM,
- CodeGenOpt::Level OptLevel);
+ CodeGenOptLevel OptLevel);
FunctionPass *createCSKYConstantIslandPass();
void initializeCSKYConstantIslandsPass(PassRegistry &);
diff --git a/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp b/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
index 1a3c9f1..c0c23a45 100644
--- a/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
+++ b/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
@@ -30,7 +30,7 @@
public:
static char ID;
- explicit CSKYDAGToDAGISel(CSKYTargetMachine &TM, CodeGenOpt::Level OptLevel)
+ explicit CSKYDAGToDAGISel(CSKYTargetMachine &TM, CodeGenOptLevel OptLevel)
: SelectionDAGISel(ID, TM, OptLevel) {}
bool runOnMachineFunction(MachineFunction &MF) override {
@@ -400,6 +400,6 @@
}
FunctionPass *llvm::createCSKYISelDag(CSKYTargetMachine &TM,
- CodeGenOpt::Level OptLevel) {
+ CodeGenOptLevel OptLevel) {
return new CSKYDAGToDAGISel(TM, OptLevel);
}
diff --git a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
index c5a57f3..8c268dc 100644
--- a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
+++ b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
@@ -53,7 +53,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
RM.value_or(Reloc::Static),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
diff --git a/llvm/lib/Target/CSKY/CSKYTargetMachine.h b/llvm/lib/Target/CSKY/CSKYTargetMachine.h
index 13d4212..e47b514 100644
--- a/llvm/lib/Target/CSKY/CSKYTargetMachine.h
+++ b/llvm/lib/Target/CSKY/CSKYTargetMachine.h
@@ -28,7 +28,7 @@
CSKYTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
diff --git a/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp b/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
index 1111bb8..d5cb488 100644
--- a/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
+++ b/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
@@ -87,7 +87,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(T,
"e-m:e-p:32:32-i1:32-i8:8-i16:16-i32:32-i64:64-f16:16-"
"f32:32-f64:64-n8:16:32:64",
@@ -129,11 +129,11 @@
PassConfig->addCodeGenPrepare();
switch (FileType) {
- case CGFT_AssemblyFile:
+ case CodeGenFileType::AssemblyFile:
PM.add(createDXILPrettyPrinterPass(Out));
PM.add(createPrintModulePass(Out, "", true));
break;
- case CGFT_ObjectFile:
+ case CodeGenFileType::ObjectFile:
if (TargetPassConfig::willCompleteCodeGenPipeline()) {
PM.add(createDXILEmbedderPass());
// We embed the other DXContainer globals after embedding DXIL so that the
@@ -149,7 +149,7 @@
} else
PM.add(createDXILWriterPass(Out));
break;
- case CGFT_Null:
+ case CodeGenFileType::Null:
break;
}
return false;
diff --git a/llvm/lib/Target/DirectX/DirectXTargetMachine.h b/llvm/lib/Target/DirectX/DirectXTargetMachine.h
index a6a1b3e..d04c375 100644
--- a/llvm/lib/Target/DirectX/DirectXTargetMachine.h
+++ b/llvm/lib/Target/DirectX/DirectXTargetMachine.h
@@ -25,7 +25,7 @@
DirectXTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
~DirectXTargetMachine() override;
diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
index 033e673..3109936 100644
--- a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
@@ -467,7 +467,7 @@
// Combine aggressively (for code size)
ShouldCombineAggressively =
- MF.getTarget().getOptLevel() <= CodeGenOpt::Default;
+ MF.getTarget().getOptLevel() <= CodeGenOptLevel::Default;
// Disable CONST64 for tiny core since it takes a LD resource.
if (!OptForSize && ST->isTinyCore())
diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
index 231ac08..812e5f7 100644
--- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
@@ -381,7 +381,7 @@
static inline bool isOptNone(const MachineFunction &MF) {
return MF.getFunction().hasOptNone() ||
- MF.getTarget().getOptLevel() == CodeGenOpt::None;
+ MF.getTarget().getOptLevel() == CodeGenOptLevel::None;
}
static inline bool isOptSize(const MachineFunction &MF) {
@@ -1156,7 +1156,7 @@
// gdb can't break at the start of the function without it. Will remove if
// this turns out to be a gdb bug.
//
- if (MF.getTarget().getOptLevel() == CodeGenOpt::None)
+ if (MF.getTarget().getOptLevel() == CodeGenOptLevel::None)
return true;
// By default we want to use SP (since it's always there). FP requires
@@ -1269,7 +1269,7 @@
int Offset = MFI.getObjectOffset(FI);
bool HasAlloca = MFI.hasVarSizedObjects();
bool HasExtraAlign = HRI.hasStackRealignment(MF);
- bool NoOpt = MF.getTarget().getOptLevel() == CodeGenOpt::None;
+ bool NoOpt = MF.getTarget().getOptLevel() == CodeGenOptLevel::None;
auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
unsigned FrameSize = MFI.getStackSize();
@@ -2584,7 +2584,7 @@
if (!hasFP(MF))
return true;
if (!isOptSize(MF) && !isMinSize(MF))
- if (MF.getTarget().getOptLevel() > CodeGenOpt::Default)
+ if (MF.getTarget().getOptLevel() > CodeGenOptLevel::Default)
return true;
// Check if CSI only has double registers, and if the registers form
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
index 4c340a42..f930015 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -59,7 +59,7 @@
/// createHexagonISelDag - This pass converts a legalized DAG into a
/// Hexagon-specific DAG, ready for instruction scheduling.
FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
- CodeGenOpt::Level OptLevel) {
+ CodeGenOptLevel OptLevel) {
return new HexagonDAGToDAGISel(TM, OptLevel);
}
}
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h
index bc65057..4ccbbf9 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h
@@ -36,7 +36,7 @@
HexagonDAGToDAGISel() = delete;
explicit HexagonDAGToDAGISel(HexagonTargetMachine &tm,
- CodeGenOpt::Level OptLevel)
+ CodeGenOptLevel OptLevel)
: SelectionDAGISel(ID, tm, OptLevel), HST(nullptr), HII(nullptr),
HRI(nullptr) {}
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
index 8917be1..1c9c258 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
@@ -429,7 +429,7 @@
/// Enable use of alias analysis during code generation (during MI
/// scheduling, DAGCombine, etc.).
bool HexagonSubtarget::useAA() const {
- if (OptLevel != CodeGenOpt::None)
+ if (OptLevel != CodeGenOptLevel::None)
return true;
return false;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.h b/llvm/lib/Target/Hexagon/HexagonSubtarget.h
index f5b4461..e56007e 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.h
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.h
@@ -70,7 +70,7 @@
public:
Hexagon::ArchEnum HexagonArchVersion;
Hexagon::ArchEnum HexagonHVXVersion = Hexagon::ArchEnum::NoArch;
- CodeGenOpt::Level OptLevel;
+ CodeGenOptLevel OptLevel;
/// True if the target should use Back-Skip-Back scheduling. This is the
/// default for V60.
bool UseBSBScheduling;
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
index 9654c9b..590e464 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
@@ -177,7 +177,7 @@
FunctionPass *createHexagonGenPredicate();
FunctionPass *createHexagonHardwareLoops();
FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
- CodeGenOpt::Level OptLevel);
+ CodeGenOptLevel OptLevel);
FunctionPass *createHexagonLoopRescheduling();
FunctionPass *createHexagonNewValueJump();
FunctionPass *createHexagonOptAddrMode();
@@ -226,7 +226,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
// Specify the vector alignment explicitly. For v512x1, the calculated
// alignment would be 512*alignment(i1), which is 512 bytes, instead of
// the required minimum of 64 bytes.
@@ -237,7 +237,7 @@
"v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
TT, CPU, FS, Options, getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM, CodeModel::Small),
- (HexagonNoOpt ? CodeGenOpt::None : OL)),
+ (HexagonNoOpt ? CodeGenOptLevel::None : OL)),
TLOF(std::make_unique<HexagonTargetObjectFile>()) {
initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
initAsmInfo();
@@ -330,7 +330,7 @@
void HexagonPassConfig::addIRPasses() {
TargetPassConfig::addIRPasses();
- bool NoOpt = (getOptLevel() == CodeGenOpt::None);
+ bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
if (!NoOpt) {
if (EnableInstSimplify)
@@ -363,7 +363,7 @@
bool HexagonPassConfig::addInstSelector() {
HexagonTargetMachine &TM = getHexagonTargetMachine();
- bool NoOpt = (getOptLevel() == CodeGenOpt::None);
+ bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
if (!NoOpt)
addPass(createHexagonOptimizeSZextends());
@@ -401,7 +401,7 @@
}
void HexagonPassConfig::addPreRegAlloc() {
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOptLevel::None) {
if (EnableCExtOpt)
addPass(createHexagonConstExtenders());
if (EnableExpandCondsets)
@@ -411,12 +411,12 @@
if (!DisableHardwareLoops)
addPass(createHexagonHardwareLoops());
}
- if (TM->getOptLevel() >= CodeGenOpt::Default)
+ if (TM->getOptLevel() >= CodeGenOptLevel::Default)
addPass(&MachinePipelinerID);
}
void HexagonPassConfig::addPostRegAlloc() {
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOptLevel::None) {
if (EnableRDFOpt)
addPass(createHexagonRDFOpt());
if (!DisableHexagonCFGOpt)
@@ -428,13 +428,13 @@
void HexagonPassConfig::addPreSched2() {
addPass(createHexagonCopyToCombine());
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOptLevel::None)
addPass(&IfConverterID);
addPass(createHexagonSplitConst32AndConst64());
}
void HexagonPassConfig::addPreEmitPass() {
- bool NoOpt = (getOptLevel() == CodeGenOpt::None);
+ bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
if (!NoOpt)
addPass(createHexagonNewValueJump());
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
index 208b47d..4ffd0fd 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
+++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
@@ -31,7 +31,7 @@
HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
~HexagonTargetMachine() override;
const HexagonSubtarget *getSubtargetImpl(const Function &F) const override;
diff --git a/llvm/lib/Target/Lanai/LanaiSubtarget.cpp b/llvm/lib/Target/Lanai/LanaiSubtarget.cpp
index 37a4843..11cd7f5 100644
--- a/llvm/lib/Target/Lanai/LanaiSubtarget.cpp
+++ b/llvm/lib/Target/Lanai/LanaiSubtarget.cpp
@@ -40,7 +40,7 @@
StringRef FeatureString, const TargetMachine &TM,
const TargetOptions & /*Options*/,
CodeModel::Model /*CodeModel*/,
- CodeGenOpt::Level /*OptLevel*/)
+ CodeGenOptLevel /*OptLevel*/)
: LanaiGenSubtargetInfo(TargetTriple, Cpu, /*TuneCPU*/ Cpu, FeatureString),
FrameLowering(initializeSubtargetDependencies(Cpu, FeatureString)),
TLInfo(TM, *this) {}
diff --git a/llvm/lib/Target/Lanai/LanaiSubtarget.h b/llvm/lib/Target/Lanai/LanaiSubtarget.h
index 7955bfe..0a22906 100644
--- a/llvm/lib/Target/Lanai/LanaiSubtarget.h
+++ b/llvm/lib/Target/Lanai/LanaiSubtarget.h
@@ -33,7 +33,7 @@
LanaiSubtarget(const Triple &TargetTriple, StringRef Cpu,
StringRef FeatureString, const TargetMachine &TM,
const TargetOptions &Options, CodeModel::Model CodeModel,
- CodeGenOpt::Level OptLevel);
+ CodeGenOptLevel OptLevel);
// ParseSubtargetFeatures - Parses features string setting specified
// subtarget options. Definition of function is auto generated by tblgen.
diff --git a/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp b/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp
index 80a6095..039182b 100644
--- a/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp
+++ b/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp
@@ -58,7 +58,7 @@
LanaiTargetMachine::LanaiTargetMachine(
const Target &T, const Triple &TT, StringRef Cpu, StringRef FeatureString,
const TargetOptions &Options, std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CodeModel, CodeGenOpt::Level OptLevel,
+ std::optional<CodeModel::Model> CodeModel, CodeGenOptLevel OptLevel,
bool JIT)
: LLVMTargetMachine(T, computeDataLayout(), TT, Cpu, FeatureString, Options,
getEffectiveRelocModel(RM),
diff --git a/llvm/lib/Target/Lanai/LanaiTargetMachine.h b/llvm/lib/Target/Lanai/LanaiTargetMachine.h
index 85e3b3f..c5c351b 100644
--- a/llvm/lib/Target/Lanai/LanaiTargetMachine.h
+++ b/llvm/lib/Target/Lanai/LanaiTargetMachine.h
@@ -32,7 +32,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CodeModel,
- CodeGenOpt::Level OptLevel, bool JIT);
+ CodeGenOptLevel OptLevel, bool JIT);
const LanaiSubtarget *
getSubtargetImpl(const llvm::Function & /*Fn*/) const override {
diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
index 46e4a06..c54a9b9 100644
--- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
@@ -78,7 +78,7 @@
LoongArchTargetMachine::LoongArchTargetMachine(
const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
const TargetOptions &Options, std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
getEffectiveRelocModel(TT, RM),
getEffectiveLoongArchCodeModel(TT, CM), OL),
@@ -159,7 +159,7 @@
//
// Run this before LSR to remove the multiplies involved in computing the
// pointer values N iterations ahead.
- if (TM->getOptLevel() != CodeGenOpt::None && EnableLoopDataPrefetch)
+ if (TM->getOptLevel() != CodeGenOptLevel::None && EnableLoopDataPrefetch)
addPass(createLoopDataPrefetchPass());
addPass(createAtomicExpandPass());
diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
index 06fcec8..7d39d47 100644
--- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
+++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
@@ -27,8 +27,8 @@
LoongArchTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT);
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
+ bool JIT);
~LoongArchTargetMachine() override;
TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
diff --git a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
index c400c9a3..e3aa9cb 100644
--- a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
+++ b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
@@ -324,7 +324,7 @@
bool M68kDAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
SDNode *Root) const {
- if (OptLevel == CodeGenOpt::None)
+ if (OptLevel == CodeGenOptLevel::None)
return false;
if (U == Root) {
diff --git a/llvm/lib/Target/M68k/M68kTargetMachine.cpp b/llvm/lib/Target/M68k/M68kTargetMachine.cpp
index 4e59e27..af8cb9a 100644
--- a/llvm/lib/Target/M68k/M68kTargetMachine.cpp
+++ b/llvm/lib/Target/M68k/M68kTargetMachine.cpp
@@ -101,7 +101,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options), TT, CPU, FS,
Options, getEffectiveRelocModel(TT, RM),
::getEffectiveCodeModel(CM, JIT), OL),
diff --git a/llvm/lib/Target/M68k/M68kTargetMachine.h b/llvm/lib/Target/M68k/M68kTargetMachine.h
index e204f63..4ff4c4c 100644
--- a/llvm/lib/Target/M68k/M68kTargetMachine.h
+++ b/llvm/lib/Target/M68k/M68kTargetMachine.h
@@ -38,7 +38,7 @@
M68kTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
~M68kTargetMachine() override;
diff --git a/llvm/lib/Target/MSP430/MSP430.h b/llvm/lib/Target/MSP430/MSP430.h
index 75fa398..60685b6 100644
--- a/llvm/lib/Target/MSP430/MSP430.h
+++ b/llvm/lib/Target/MSP430/MSP430.h
@@ -39,7 +39,7 @@
class PassRegistry;
FunctionPass *createMSP430ISelDag(MSP430TargetMachine &TM,
- CodeGenOpt::Level OptLevel);
+ CodeGenOptLevel OptLevel);
FunctionPass *createMSP430BranchSelectionPass();
diff --git a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
index cb5d9791..660861a 100644
--- a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
@@ -95,7 +95,7 @@
MSP430DAGToDAGISel() = delete;
- MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel)
+ MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOptLevel OptLevel)
: SelectionDAGISel(ID, TM, OptLevel) {}
private:
@@ -129,11 +129,10 @@
/// MSP430-specific DAG, ready for instruction scheduling.
///
FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM,
- CodeGenOpt::Level OptLevel) {
- return new MSP430DAGToDAGISel(TM, OptLevel);
+ CodeGenOptLevel OptLevel) {
+ return new MSP430DAGToDAGISel(TM, OptLevel);
}
-
/// MatchWrapper - Try to match MSP430ISD::Wrapper node into an addressing mode.
/// These wrap things that will resolve down into a symbol reference. If no
/// match is possible, this returns true, otherwise it returns false.
diff --git a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
index 2efeeb5..39e0658 100644
--- a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
+++ b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
@@ -43,7 +43,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options), TT, CPU, FS,
Options, getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
diff --git a/llvm/lib/Target/MSP430/MSP430TargetMachine.h b/llvm/lib/Target/MSP430/MSP430TargetMachine.h
index 30e1f7f..f9af9a7 100644
--- a/llvm/lib/Target/MSP430/MSP430TargetMachine.h
+++ b/llvm/lib/Target/MSP430/MSP430TargetMachine.h
@@ -31,7 +31,7 @@
MSP430TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
~MSP430TargetMachine() override;
diff --git a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
index c8c9612..0be9b94 100644
--- a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
@@ -220,6 +220,6 @@
}
FunctionPass *llvm::createMips16ISelDag(MipsTargetMachine &TM,
- CodeGenOpt::Level OptLevel) {
+ CodeGenOptLevel OptLevel) {
return new Mips16DAGToDAGISel(TM, OptLevel);
}
diff --git a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h
index 1ef1940..c6d3bde 100644
--- a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h
+++ b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h
@@ -19,7 +19,7 @@
class Mips16DAGToDAGISel : public MipsDAGToDAGISel {
public:
- explicit Mips16DAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL)
+ explicit Mips16DAGToDAGISel(MipsTargetMachine &TM, CodeGenOptLevel OL)
: MipsDAGToDAGISel(TM, OL) {}
private:
@@ -48,7 +48,7 @@
};
FunctionPass *createMips16ISelDag(MipsTargetMachine &TM,
- CodeGenOpt::Level OptLevel);
+ CodeGenOptLevel OptLevel);
}
#endif
diff --git a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
index 8aa5f76..cb98c04 100644
--- a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
+++ b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
@@ -610,7 +610,8 @@
continue;
// Delay slot filling is disabled at -O0, or in microMIPS32R6.
- if (!DisableDelaySlotFiller && (TM->getOptLevel() != CodeGenOpt::None) &&
+ if (!DisableDelaySlotFiller &&
+ (TM->getOptLevel() != CodeGenOptLevel::None) &&
!(InMicroMipsMode && STI.hasMips32r6())) {
bool Filled = false;
diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.h b/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
index 9c86101..e41cb08 100644
--- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
+++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.h
@@ -34,7 +34,7 @@
MipsDAGToDAGISel() = delete;
- explicit MipsDAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL)
+ explicit MipsDAGToDAGISel(MipsTargetMachine &TM, CodeGenOptLevel OL)
: SelectionDAGISel(ID, TM, OL), Subtarget(nullptr) {}
bool runOnMachineFunction(MachineFunction &MF) override;
diff --git a/llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp b/llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp
index 3d970d6..0578655 100644
--- a/llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp
@@ -131,7 +131,7 @@
auto *TPC = &getAnalysis<TargetPassConfig>();
const Function &F = MF.getFunction();
bool EnableOpt =
- MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
+ MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !skipFunction(F);
const MipsSubtarget &ST = MF.getSubtarget<MipsSubtarget>();
const MipsLegalizerInfo *LI =
diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
index 0bb16f3..8c865af 100644
--- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
@@ -1442,6 +1442,6 @@
}
FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM,
- CodeGenOpt::Level OptLevel) {
+ CodeGenOptLevel OptLevel) {
return new MipsSEDAGToDAGISel(TM, OptLevel);
}
diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h
index f3b8872..96dc876 100644
--- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h
+++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h
@@ -20,7 +20,7 @@
class MipsSEDAGToDAGISel : public MipsDAGToDAGISel {
public:
- explicit MipsSEDAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL)
+ explicit MipsSEDAGToDAGISel(MipsTargetMachine &TM, CodeGenOptLevel OL)
: MipsDAGToDAGISel(TM, OL) {}
private:
@@ -140,7 +140,7 @@
};
FunctionPass *createMipsSEISelDag(MipsTargetMachine &TM,
- CodeGenOpt::Level OptLevel);
+ CodeGenOptLevel OptLevel);
}
#endif
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp
index 323e611..0134fcb 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.cpp
+++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp
@@ -234,8 +234,8 @@
: &Mips::GPR32RegClass);
}
-CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
- return CodeGenOpt::Aggressive;
+CodeGenOptLevel MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
+ return CodeGenOptLevel::Aggressive;
}
MipsSubtarget &
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.h b/llvm/lib/Target/Mips/MipsSubtarget.h
index ec8ca64..014c950 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.h
+++ b/llvm/lib/Target/Mips/MipsSubtarget.h
@@ -228,7 +228,7 @@
/// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
bool enablePostRAScheduler() const override;
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
- CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
+ CodeGenOptLevel getOptLevelToEnablePostRAScheduler() const override;
bool isABI_N64() const;
bool isABI_N32() const;
diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
index fe31ab9..0742228 100644
--- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp
+++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
@@ -123,7 +123,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT,
+ CodeGenOptLevel OL, bool JIT,
bool isLittle)
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
CPU, FS, Options, getEffectiveRelocModel(JIT, RM),
@@ -152,7 +152,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
void MipselTargetMachine::anchor() {}
@@ -162,7 +162,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
const MipsSubtarget *
@@ -347,7 +347,7 @@
}
void MipsPassConfig::addPreRegBankSelect() {
- bool IsOptNone = getOptLevel() == CodeGenOpt::None;
+ bool IsOptNone = getOptLevel() == CodeGenOptLevel::None;
addPass(createMipsPostLegalizeCombiner(IsOptNone));
}
diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.h b/llvm/lib/Target/Mips/MipsTargetMachine.h
index d07e5bb..0ad239e 100644
--- a/llvm/lib/Target/Mips/MipsTargetMachine.h
+++ b/llvm/lib/Target/Mips/MipsTargetMachine.h
@@ -40,7 +40,7 @@
MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT, bool isLittle);
~MipsTargetMachine() override;
@@ -89,7 +89,7 @@
MipsebTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
};
@@ -102,7 +102,7 @@
MipselTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
};
diff --git a/llvm/lib/Target/NVPTX/NVPTX.h b/llvm/lib/Target/NVPTX/NVPTX.h
index ec32a95..c5816b9 100644
--- a/llvm/lib/Target/NVPTX/NVPTX.h
+++ b/llvm/lib/Target/NVPTX/NVPTX.h
@@ -36,7 +36,7 @@
}
FunctionPass *createNVPTXISelDag(NVPTXTargetMachine &TM,
- llvm::CodeGenOpt::Level OptLevel);
+ llvm::CodeGenOptLevel OptLevel);
ModulePass *createNVPTXAssignValidGlobalNamesPass();
ModulePass *createGenericToNVVMLegacyPass();
ModulePass *createNVPTXCtorDtorLoweringLegacyPass();
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
index 62991df..0aef259 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -32,7 +32,7 @@
/// createNVPTXISelDag - This pass converts a legalized DAG into a
/// NVPTX-specific DAG, ready for instruction scheduling.
FunctionPass *llvm::createNVPTXISelDag(NVPTXTargetMachine &TM,
- llvm::CodeGenOpt::Level OptLevel) {
+ llvm::CodeGenOptLevel OptLevel) {
return new NVPTXDAGToDAGISel(TM, OptLevel);
}
@@ -41,9 +41,9 @@
INITIALIZE_PASS(NVPTXDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
- CodeGenOpt::Level OptLevel)
+ CodeGenOptLevel OptLevel)
: SelectionDAGISel(ID, tm, OptLevel), TM(tm) {
- doMulWide = (OptLevel > 0);
+ doMulWide = (OptLevel > CodeGenOptLevel::None);
}
bool NVPTXDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
index b283dc9..0692233 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
@@ -43,8 +43,7 @@
NVPTXDAGToDAGISel() = delete;
- explicit NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
- CodeGenOpt::Level OptLevel);
+ explicit NVPTXDAGToDAGISel(NVPTXTargetMachine &tm, CodeGenOptLevel OptLevel);
bool runOnMachineFunction(MachineFunction &MF) override;
const NVPTXSubtarget *Subtarget = nullptr;
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index 8b2d919..e4d5e5c 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -4804,13 +4804,13 @@
//===----------------------------------------------------------------------===//
bool NVPTXTargetLowering::allowFMA(MachineFunction &MF,
- CodeGenOpt::Level OptLevel) const {
+ CodeGenOptLevel OptLevel) const {
// Always honor command-line argument
if (FMAContractLevelOpt.getNumOccurrences() > 0)
return FMAContractLevelOpt > 0;
// Do not contract if we're not optimizing the code.
- if (OptLevel == 0)
+ if (OptLevel == CodeGenOptLevel::None)
return false;
// Honor TargetOptions flags that explicitly say fusion is okay.
@@ -4834,10 +4834,9 @@
/// operands N0 and N1. This is a helper for PerformADDCombine that is
/// called with the default operands, and if that fails, with commuted
/// operands.
-static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
- TargetLowering::DAGCombinerInfo &DCI,
- const NVPTXSubtarget &Subtarget,
- CodeGenOpt::Level OptLevel) {
+static SDValue PerformADDCombineWithOperands(
+ SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI,
+ const NVPTXSubtarget &Subtarget, CodeGenOptLevel OptLevel) {
SelectionDAG &DAG = DCI.DAG;
// Skip non-integer, non-scalar case
EVT VT=N0.getValueType();
@@ -4852,7 +4851,7 @@
// Since integer multiply-add costs the same as integer multiply
// but is more costly than integer add, do the fusion only when
// the mul is only used in the add.
- if (OptLevel==CodeGenOpt::None || VT != MVT::i32 ||
+ if (OptLevel == CodeGenOptLevel::None || VT != MVT::i32 ||
!N0.getNode()->hasOneUse())
return SDValue();
@@ -4949,7 +4948,7 @@
static SDValue PerformADDCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI,
const NVPTXSubtarget &Subtarget,
- CodeGenOpt::Level OptLevel) {
+ CodeGenOptLevel OptLevel) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
@@ -5039,11 +5038,11 @@
static SDValue PerformREMCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI,
- CodeGenOpt::Level OptLevel) {
+ CodeGenOptLevel OptLevel) {
assert(N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM);
// Don't do anything at less than -O2.
- if (OptLevel < CodeGenOpt::Default)
+ if (OptLevel < CodeGenOptLevel::Default)
return SDValue();
SelectionDAG &DAG = DCI.DAG;
@@ -5209,8 +5208,8 @@
/// PerformMULCombine - Runs PTX-specific DAG combine patterns on MUL nodes.
static SDValue PerformMULCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI,
- CodeGenOpt::Level OptLevel) {
- if (OptLevel > 0) {
+ CodeGenOptLevel OptLevel) {
+ if (OptLevel > CodeGenOptLevel::None) {
// Try mul.wide combining at OptLevel > 0
if (SDValue Ret = TryMULWIDECombine(N, DCI))
return Ret;
@@ -5222,8 +5221,8 @@
/// PerformSHLCombine - Runs PTX-specific DAG combine patterns on SHL nodes.
static SDValue PerformSHLCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI,
- CodeGenOpt::Level OptLevel) {
- if (OptLevel > 0) {
+ CodeGenOptLevel OptLevel) {
+ if (OptLevel > CodeGenOptLevel::None) {
// Try mul.wide combining at OptLevel > 0
if (SDValue Ret = TryMULWIDECombine(N, DCI))
return Ret;
@@ -5255,7 +5254,7 @@
SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
- CodeGenOpt::Level OptLevel = getTargetMachine().getOptLevel();
+ CodeGenOptLevel OptLevel = getTargetMachine().getOptLevel();
switch (N->getOpcode()) {
default: break;
case ISD::ADD:
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.h b/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
index 87cd52c..0b760d0 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
@@ -556,7 +556,7 @@
unsigned combineRepeatedFPDivisors() const override { return 2; }
- bool allowFMA(MachineFunction &MF, CodeGenOpt::Level OptLevel) const;
+ bool allowFMA(MachineFunction &MF, CodeGenOptLevel OptLevel) const;
bool allowUnsafeFPMath(MachineFunction &MF) const;
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
index 1892f95..cad97b1 100644
--- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
@@ -133,7 +133,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool is64bit)
+ CodeGenOptLevel OL, bool is64bit)
// The pic relocation model is used regardless of what the client has
// specified, as it is the only relocation model currently supported.
: LLVMTargetMachine(T, computeDataLayout(is64bit, UseShortPointersOpt), TT,
@@ -161,7 +161,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
: NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
void NVPTXTargetMachine64::anchor() {}
@@ -171,7 +171,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
: NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
namespace {
@@ -310,7 +310,7 @@
}
void NVPTXPassConfig::addEarlyCSEOrGVNPass() {
- if (getOptLevel() == CodeGenOpt::Aggressive)
+ if (getOptLevel() == CodeGenOptLevel::Aggressive)
addPass(createGVNPass());
else
addPass(createEarlyCSEPass());
@@ -373,7 +373,7 @@
const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
addPass(createNVVMReflectPass(ST.getSmVersion()));
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOptLevel::None)
addPass(createNVPTXImageOptimizerPass());
addPass(createNVPTXAssignValidGlobalNamesPass());
addPass(createGenericToNVVMLegacyPass());
@@ -381,7 +381,7 @@
// NVPTXLowerArgs is required for correctness and should be run right
// before the address space inference passes.
addPass(createNVPTXLowerArgsPass());
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOptLevel::None) {
addAddressSpaceInferencePasses();
addStraightLineScalarOptimizationPasses();
}
@@ -403,7 +403,7 @@
// %1 = shl %a, 2
//
// but EarlyCSE can do neither of them.
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOptLevel::None) {
addEarlyCSEOrGVNPass();
if (!DisableLoadStoreVectorizer)
addPass(createLoadStoreVectorizerPass());
@@ -434,7 +434,7 @@
void NVPTXPassConfig::addPostRegAlloc() {
addPass(createNVPTXPrologEpilogPass());
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOptLevel::None) {
// NVPTXPrologEpilogPass calculates frame object offset and replace frame
// index with VRFrame register. NVPTXPeephole need to be run after that and
// will replace VRFrame with VRFrameLocal when possible.
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h
index 25dfea1..cfdd8da 100644
--- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h
+++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h
@@ -38,7 +38,7 @@
NVPTXTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OP,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OP,
bool is64bit);
~NVPTXTargetMachine() override;
const NVPTXSubtarget *getSubtargetImpl(const Function &) const override {
@@ -88,7 +88,7 @@
NVPTXTargetMachine32(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
};
@@ -99,7 +99,7 @@
NVPTXTargetMachine64(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
};
diff --git a/llvm/lib/Target/PowerPC/PPC.h b/llvm/lib/Target/PowerPC/PPC.h
index ad62a47..086b61a 100644
--- a/llvm/lib/Target/PowerPC/PPC.h
+++ b/llvm/lib/Target/PowerPC/PPC.h
@@ -46,7 +46,7 @@
FunctionPass *createPPCMIPeepholePass();
FunctionPass *createPPCBranchSelectionPass();
FunctionPass *createPPCBranchCoalescingPass();
- FunctionPass *createPPCISelDag(PPCTargetMachine &TM, CodeGenOpt::Level OL);
+ FunctionPass *createPPCISelDag(PPCTargetMachine &TM, CodeGenOptLevel OL);
FunctionPass *createPPCTLSDynamicCallPass();
FunctionPass *createPPCBoolRetToIntPass();
FunctionPass *createPPCExpandISELPass();
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 1c2f562..b57d185 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -151,7 +151,7 @@
PPCDAGToDAGISel() = delete;
- explicit PPCDAGToDAGISel(PPCTargetMachine &tm, CodeGenOpt::Level OptLevel)
+ explicit PPCDAGToDAGISel(PPCTargetMachine &tm, CodeGenOptLevel OptLevel)
: SelectionDAGISel(ID, tm, OptLevel), TM(tm) {}
bool runOnMachineFunction(MachineFunction &MF) override {
@@ -756,8 +756,8 @@
static bool canOptimizeTLSDFormToXForm(SelectionDAG *CurDAG, SDValue Base) {
// Do not do this transformation at -O0.
- if (CurDAG->getTarget().getOptLevel() == CodeGenOpt::None)
- return false;
+ if (CurDAG->getTarget().getOptLevel() == CodeGenOptLevel::None)
+ return false;
// In order to perform this optimization inside tryTLSXForm[Load|Store],
// Base is expected to be an ADD_TLS node.
@@ -4055,7 +4055,7 @@
// This optimization will emit code that assumes 64-bit registers
// so we don't want to run it in 32-bit mode. Also don't run it
// on functions that are not to be optimized.
- if (TM.getOptLevel() == CodeGenOpt::None || !TM.isPPC64())
+ if (TM.getOptLevel() == CodeGenOptLevel::None || !TM.isPPC64())
return false;
// For POWER10, it is more profitable to use the set boolean extension
@@ -6667,7 +6667,7 @@
/// on the DAG representation.
void PPCDAGToDAGISel::PostprocessISelDAG() {
// Skip peepholes at -O0.
- if (TM.getOptLevel() == CodeGenOpt::None)
+ if (TM.getOptLevel() == CodeGenOptLevel::None)
return;
PeepholePPC64();
@@ -7792,6 +7792,6 @@
/// PowerPC-specific DAG, ready for instruction scheduling.
///
FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM,
- CodeGenOpt::Level OptLevel) {
+ CodeGenOptLevel OptLevel) {
return new PPCDAGToDAGISel(TM, OptLevel);
}
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 95f2243..f4e3531 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -399,7 +399,7 @@
// MASS transformation for LLVM intrinsics with replicating fast-math flag
// to be consistent to PPCGenScalarMASSEntries pass
- if (TM.getOptLevel() == CodeGenOpt::Aggressive) {
+ if (TM.getOptLevel() == CodeGenOptLevel::Aggressive) {
setOperationAction(ISD::FSIN , MVT::f64, Custom);
setOperationAction(ISD::FCOS , MVT::f64, Custom);
setOperationAction(ISD::FPOW , MVT::f64, Custom);
@@ -17134,7 +17134,7 @@
/// target-independent logic.
EVT PPCTargetLowering::getOptimalMemOpType(
const MemOp &Op, const AttributeList &FuncAttributes) const {
- if (getTargetMachine().getOptLevel() != CodeGenOpt::None) {
+ if (getTargetMachine().getOptLevel() != CodeGenOptLevel::None) {
// We should use Altivec/VSX loads and stores when available. For unaligned
// addresses, unaligned VSX loads are only fast starting with the P8.
if (Subtarget.hasAltivec() && Op.size() >= 16) {
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 6ca68ec..854034b 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -763,7 +763,7 @@
bool DoRegPressureReduce) const {
// Using the machine combiner in this way is potentially expensive, so
// restrict to when aggressive optimizations are desired.
- if (Subtarget.getTargetMachine().getOptLevel() != CodeGenOpt::Aggressive)
+ if (Subtarget.getTargetMachine().getOptLevel() != CodeGenOptLevel::Aggressive)
return false;
if (getFMAPatterns(Root, Patterns, DoRegPressureReduce))
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index eaef4bf..42f052c 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -197,7 +197,7 @@
return Ret;
}
-static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL,
+static std::string computeFSAdditions(StringRef FS, CodeGenOptLevel OL,
const Triple &TT) {
std::string FullFS = std::string(FS);
@@ -209,14 +209,14 @@
FullFS = "+64bit";
}
- if (OL >= CodeGenOpt::Default) {
+ if (OL >= CodeGenOptLevel::Default) {
if (!FullFS.empty())
FullFS = "+crbits," + FullFS;
else
FullFS = "+crbits";
}
- if (OL != CodeGenOpt::None) {
+ if (OL != CodeGenOptLevel::None) {
if (!FullFS.empty())
FullFS = "+invariant-function-descriptors," + FullFS;
else
@@ -345,7 +345,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
computeFSAdditions(FS, OL, TT), Options,
getEffectiveRelocModel(TT, RM),
@@ -414,7 +414,7 @@
: TargetPassConfig(TM, PM) {
// At any optimization level above -O0 we use the Machine Scheduler and not
// the default Post RA List Scheduler.
- if (TM.getOptLevel() != CodeGenOpt::None)
+ if (TM.getOptLevel() != CodeGenOptLevel::None)
substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
}
@@ -454,7 +454,7 @@
}
void PPCPassConfig::addIRPasses() {
- if (TM->getOptLevel() != CodeGenOpt::None)
+ if (TM->getOptLevel() != CodeGenOptLevel::None)
addPass(createPPCBoolRetToIntPass());
addPass(createAtomicExpandPass());
@@ -463,7 +463,7 @@
// Generate PowerPC target-specific entries for scalar math functions
// that are available in IBM MASS (scalar) library.
- if (TM->getOptLevel() == CodeGenOpt::Aggressive &&
+ if (TM->getOptLevel() == CodeGenOptLevel::Aggressive &&
EnablePPCGenScalarMASSEntries) {
TM->Options.PPCGenScalarMASSEntries = EnablePPCGenScalarMASSEntries;
addPass(createPPCGenScalarMASSEntriesPass());
@@ -473,7 +473,7 @@
if (EnablePrefetch.getNumOccurrences() > 0)
addPass(createLoopDataPrefetchPass());
- if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
+ if (TM->getOptLevel() >= CodeGenOptLevel::Default && EnableGEPOpt) {
// Call SeparateConstOffsetFromGEP pass to extract constants within indices
// and lower a GEP with multiple indices to either arithmetic operations or
// multiple GEPs with single index.
@@ -490,13 +490,13 @@
}
bool PPCPassConfig::addPreISel() {
- if (MergeStringPool && getOptLevel() != CodeGenOpt::None)
+ if (MergeStringPool && getOptLevel() != CodeGenOptLevel::None)
addPass(createPPCMergeStringPoolPass());
- if (!DisableInstrFormPrep && getOptLevel() != CodeGenOpt::None)
+ if (!DisableInstrFormPrep && getOptLevel() != CodeGenOptLevel::None)
addPass(createPPCLoopInstrFormPrepPass(getPPCTargetMachine()));
- if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
+ if (!DisableCTRLoops && getOptLevel() != CodeGenOptLevel::None)
addPass(createHardwareLoopsLegacyPass());
return false;
@@ -516,7 +516,7 @@
addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
#ifndef NDEBUG
- if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
+ if (!DisableCTRLoops && getOptLevel() != CodeGenOptLevel::None)
addPass(createPPCCTRLoopsVerify());
#endif
@@ -527,12 +527,12 @@
void PPCPassConfig::addMachineSSAOptimization() {
// Run CTR loops pass before any cfg modification pass to prevent the
// canonical form of hardware loop from being destroied.
- if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
+ if (!DisableCTRLoops && getOptLevel() != CodeGenOptLevel::None)
addPass(createPPCCTRLoopsPass());
// PPCBranchCoalescingPass need to be done before machine sinking
// since it merges empty blocks.
- if (EnableBranchCoalescing && getOptLevel() != CodeGenOpt::None)
+ if (EnableBranchCoalescing && getOptLevel() != CodeGenOptLevel::None)
addPass(createPPCBranchCoalescingPass());
TargetPassConfig::addMachineSSAOptimization();
// For little endian, remove where possible the vector swap instructions
@@ -541,7 +541,7 @@
!DisableVSXSwapRemoval)
addPass(createPPCVSXSwapRemovalPass());
// Reduce the number of cr-logical ops.
- if (ReduceCRLogical && getOptLevel() != CodeGenOpt::None)
+ if (ReduceCRLogical && getOptLevel() != CodeGenOptLevel::None)
addPass(createPPCReduceCRLogicalsPass());
// Target-specific peephole cleanups performed after instruction
// selection.
@@ -552,7 +552,7 @@
}
void PPCPassConfig::addPreRegAlloc() {
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOptLevel::None) {
initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
&PPCVSXFMAMutateID);
@@ -570,12 +570,12 @@
if (EnableExtraTOCRegDeps)
addPass(createPPCTOCRegDepsPass());
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOptLevel::None)
addPass(&MachinePipelinerID);
}
void PPCPassConfig::addPreSched2() {
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOptLevel::None)
addPass(&IfConverterID);
}
@@ -583,7 +583,7 @@
addPass(createPPCPreEmitPeepholePass());
addPass(createPPCExpandISELPass());
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOptLevel::None)
addPass(createPPCEarlyReturnPass());
}
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.h b/llvm/lib/Target/PowerPC/PPCTargetMachine.h
index 5d4571b..56145a2 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.h
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.h
@@ -39,7 +39,7 @@
PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
~PPCTargetMachine() override;
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
index 107ca51..e66d967 100644
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -34,7 +34,7 @@
void initializeRISCVCodeGenPreparePass(PassRegistry &);
FunctionPass *createRISCVISelDag(RISCVTargetMachine &TM,
- CodeGenOpt::Level OptLevel);
+ CodeGenOptLevel OptLevel);
FunctionPass *createRISCVMakeCompressibleOptPass();
void initializeRISCVMakeCompressibleOptPass(PassRegistry &);
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index d5c1ab4..e6d0346 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3653,7 +3653,7 @@
// This pass converts a legalized DAG into a RISCV-specific DAG, ready
// for instruction scheduling.
FunctionPass *llvm::createRISCVISelDag(RISCVTargetMachine &TM,
- CodeGenOpt::Level OptLevel) {
+ CodeGenOptLevel OptLevel) {
return new RISCVDAGToDAGISel(TM, OptLevel);
}
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
index b9117a4..c220b2d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -30,7 +30,7 @@
RISCVDAGToDAGISel() = delete;
explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine,
- CodeGenOpt::Level OptLevel)
+ CodeGenOptLevel OptLevel)
: SelectionDAGISel(ID, TargetMachine, OptLevel) {}
bool runOnMachineFunction(MachineFunction &MF) override {
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index d4fd66c..8c15d17 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -109,7 +109,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
getEffectiveRelocModel(TT, RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
@@ -284,7 +284,7 @@
void RISCVPassConfig::addIRPasses() {
addPass(createAtomicExpandPass());
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOptLevel::None) {
addPass(createRISCVGatherScatterLoweringPass());
addPass(createInterleavedAccessPass());
addPass(createRISCVCodeGenPreparePass());
@@ -294,7 +294,7 @@
}
bool RISCVPassConfig::addPreISel() {
- if (TM->getOptLevel() != CodeGenOpt::None) {
+ if (TM->getOptLevel() != CodeGenOptLevel::None) {
// Add a barrier before instruction selection so that we will not get
// deleted block address after enabling default outlining. See D99707 for
// more details.
@@ -350,12 +350,13 @@
// propagation after the machine outliner (which runs after addPreEmitPass)
// currently leads to incorrect code-gen, where copies to registers within
// outlined functions are removed erroneously.
- if (TM->getOptLevel() >= CodeGenOpt::Default && EnableRISCVCopyPropagation)
+ if (TM->getOptLevel() >= CodeGenOptLevel::Default &&
+ EnableRISCVCopyPropagation)
addPass(createMachineCopyPropagationPass(true));
}
void RISCVPassConfig::addPreEmitPass2() {
- if (TM->getOptLevel() != CodeGenOpt::None) {
+ if (TM->getOptLevel() != CodeGenOptLevel::None) {
addPass(createRISCVMoveMergePass());
// Schedule PushPop Optimization before expansion of Pseudo instruction,
// ensuring return instruction is detected correctly.
@@ -386,7 +387,7 @@
void RISCVPassConfig::addPreRegAlloc() {
addPass(createRISCVPreRAExpandPseudoPass());
- if (TM->getOptLevel() != CodeGenOpt::None)
+ if (TM->getOptLevel() != CodeGenOptLevel::None)
addPass(createRISCVMergeBaseOffsetOptPass());
addPass(createRISCVInsertVSETVLIPass());
addPass(createRISCVInsertReadWriteCSRPass());
@@ -405,7 +406,8 @@
void RISCVPassConfig::addPostRegAlloc() {
- if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
+ if (TM->getOptLevel() != CodeGenOptLevel::None &&
+ EnableRedundantCopyElimination)
addPass(createRISCVRedundantCopyEliminationPass());
}
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.h b/llvm/lib/Target/RISCV/RISCVTargetMachine.h
index 7754220..68dfb3c 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.h
@@ -29,7 +29,7 @@
RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
const RISCVSubtarget *getSubtargetImpl(const Function &F) const override;
diff --git a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
index 9ca291b..14dd429 100644
--- a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
@@ -72,7 +72,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
diff --git a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.h b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.h
index cb16d7a0..a1a9f26 100644
--- a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.h
+++ b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.h
@@ -26,7 +26,7 @@
SPIRVTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
const SPIRVSubtarget *getSubtargetImpl() const { return &Subtarget; }
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
index 577dc13..6e146fa3 100644
--- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -100,7 +100,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT,
+ CodeGenOptLevel OL, bool JIT,
bool is64bit)
: LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
getEffectiveRelocModel(RM),
@@ -210,7 +210,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
void SparcV9TargetMachine::anchor() { }
@@ -220,7 +220,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
void SparcelTargetMachine::anchor() {}
@@ -230,5 +230,5 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.h b/llvm/lib/Target/Sparc/SparcTargetMachine.h
index 6e3c8e7..0493829 100644
--- a/llvm/lib/Target/Sparc/SparcTargetMachine.h
+++ b/llvm/lib/Target/Sparc/SparcTargetMachine.h
@@ -30,7 +30,7 @@
SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT, bool is64bit);
~SparcTargetMachine() override;
@@ -57,7 +57,7 @@
SparcV8TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
};
@@ -70,7 +70,7 @@
SparcV9TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
};
@@ -81,7 +81,7 @@
SparcelTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
};
diff --git a/llvm/lib/Target/SystemZ/SystemZ.h b/llvm/lib/Target/SystemZ/SystemZ.h
index cdd2850..d7aa9e4 100644
--- a/llvm/lib/Target/SystemZ/SystemZ.h
+++ b/llvm/lib/Target/SystemZ/SystemZ.h
@@ -189,7 +189,7 @@
} // end namespace SystemZ
FunctionPass *createSystemZISelDag(SystemZTargetMachine &TM,
- CodeGenOpt::Level OptLevel);
+ CodeGenOptLevel OptLevel);
FunctionPass *createSystemZElimComparePass(SystemZTargetMachine &TM);
FunctionPass *createSystemZShortenInstPass(SystemZTargetMachine &TM);
FunctionPass *createSystemZLongBranchPass(SystemZTargetMachine &TM);
diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index f88e365..4cc6953 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -350,7 +350,7 @@
SystemZDAGToDAGISel() = delete;
- SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
+ SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOptLevel OptLevel)
: SelectionDAGISel(ID, TM, OptLevel) {}
bool runOnMachineFunction(MachineFunction &MF) override {
@@ -384,7 +384,7 @@
INITIALIZE_PASS(SystemZDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM,
- CodeGenOpt::Level OptLevel) {
+ CodeGenOptLevel OptLevel) {
return new SystemZDAGToDAGISel(TM, OptLevel);
}
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
index 787c516..7a3a2a7 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
@@ -143,7 +143,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(
T, computeDataLayout(TT), TT, CPU, FS, Options,
getEffectiveRelocModel(RM),
@@ -221,7 +221,7 @@
} // end anonymous namespace
void SystemZPassConfig::addIRPasses() {
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOptLevel::None) {
addPass(createSystemZTDCPass());
addPass(createLoopDataPrefetchPass());
}
@@ -232,7 +232,7 @@
bool SystemZPassConfig::addInstSelector() {
addPass(createSystemZISelDag(getSystemZTargetMachine(), getOptLevel()));
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOptLevel::None)
addPass(createSystemZLDCleanupPass(getSystemZTargetMachine()));
return false;
@@ -254,12 +254,12 @@
void SystemZPassConfig::addPostRegAlloc() {
// PostRewrite needs to be run at -O0 also (in which case addPostRewrite()
// is not called).
- if (getOptLevel() == CodeGenOpt::None)
+ if (getOptLevel() == CodeGenOptLevel::None)
addPass(createSystemZPostRewritePass(getSystemZTargetMachine()));
}
void SystemZPassConfig::addPreSched2() {
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOptLevel::None)
addPass(&IfConverterID);
}
@@ -267,7 +267,7 @@
// Do instruction shortening before compare elimination because some
// vector instructions will be shortened into opcodes that compare
// elimination recognizes.
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOptLevel::None)
addPass(createSystemZShortenInstPass(getSystemZTargetMachine()));
// We eliminate comparisons here rather than earlier because some
@@ -293,14 +293,14 @@
// Doing it so late makes it more likely that a register will be reused
// between the comparison and the branch, but it isn't clear whether
// preventing that would be a win or not.
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOptLevel::None)
addPass(createSystemZElimComparePass(getSystemZTargetMachine()));
addPass(createSystemZLongBranchPass(getSystemZTargetMachine()));
// Do final scheduling after all other optimizations, to get an
// optimal input for the decoder (branch relaxation must happen
// after block placement).
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOptLevel::None)
addPass(&PostMachineSchedulerID);
}
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h
index 20d68ff..75e5d68 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h
+++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h
@@ -33,7 +33,7 @@
SystemZTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
~SystemZTargetMachine() override;
diff --git a/llvm/lib/Target/TargetMachine.cpp b/llvm/lib/Target/TargetMachine.cpp
index 323b7c0..0b4a251 100644
--- a/llvm/lib/Target/TargetMachine.cpp
+++ b/llvm/lib/Target/TargetMachine.cpp
@@ -198,9 +198,9 @@
}
/// Returns the optimization level: None, Less, Default, or Aggressive.
-CodeGenOpt::Level TargetMachine::getOptLevel() const { return OptLevel; }
+CodeGenOptLevel TargetMachine::getOptLevel() const { return OptLevel; }
-void TargetMachine::setOptLevel(CodeGenOpt::Level Level) { OptLevel = Level; }
+void TargetMachine::setOptLevel(CodeGenOptLevel Level) { OptLevel = Level; }
TargetTransformInfo
TargetMachine::getTargetTransformInfo(const Function &F) const {
diff --git a/llvm/lib/Target/TargetMachineC.cpp b/llvm/lib/Target/TargetMachineC.cpp
index 7cd29b4..d418377 100644
--- a/llvm/lib/Target/TargetMachineC.cpp
+++ b/llvm/lib/Target/TargetMachineC.cpp
@@ -127,19 +127,19 @@
bool JIT;
std::optional<CodeModel::Model> CM = unwrap(CodeModel, JIT);
- CodeGenOpt::Level OL;
+ CodeGenOptLevel OL;
switch (Level) {
case LLVMCodeGenLevelNone:
- OL = CodeGenOpt::None;
+ OL = CodeGenOptLevel::None;
break;
case LLVMCodeGenLevelLess:
- OL = CodeGenOpt::Less;
+ OL = CodeGenOptLevel::Less;
break;
case LLVMCodeGenLevelAggressive:
- OL = CodeGenOpt::Aggressive;
+ OL = CodeGenOptLevel::Aggressive;
break;
default:
- OL = CodeGenOpt::Default;
+ OL = CodeGenOptLevel::Default;
break;
}
@@ -195,10 +195,10 @@
CodeGenFileType ft;
switch (codegen) {
case LLVMAssemblyFile:
- ft = CGFT_AssemblyFile;
+ ft = CodeGenFileType::AssemblyFile;
break;
default:
- ft = CGFT_ObjectFile;
+ ft = CodeGenFileType::ObjectFile;
break;
}
if (TM->addPassesToEmitFile(pass, OS, nullptr, ft)) {
diff --git a/llvm/lib/Target/VE/VETargetMachine.cpp b/llvm/lib/Target/VE/VETargetMachine.cpp
index 93fb3d8..6d102bf 100644
--- a/llvm/lib/Target/VE/VETargetMachine.cpp
+++ b/llvm/lib/Target/VE/VETargetMachine.cpp
@@ -88,7 +88,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
diff --git a/llvm/lib/Target/VE/VETargetMachine.h b/llvm/lib/Target/VE/VETargetMachine.h
index 057ff16..fd83829 100644
--- a/llvm/lib/Target/VE/VETargetMachine.h
+++ b/llvm/lib/Target/VE/VETargetMachine.h
@@ -31,7 +31,7 @@
VETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
~VETargetMachine() override;
diff --git a/llvm/lib/Target/WebAssembly/WebAssembly.h b/llvm/lib/Target/WebAssembly/WebAssembly.h
index 53be8f5..91765ad 100644
--- a/llvm/lib/Target/WebAssembly/WebAssembly.h
+++ b/llvm/lib/Target/WebAssembly/WebAssembly.h
@@ -33,7 +33,7 @@
// ISel and immediate followup passes.
FunctionPass *createWebAssemblyISelDag(WebAssemblyTargetMachine &TM,
- CodeGenOpt::Level OptLevel);
+ CodeGenOptLevel OptLevel);
FunctionPass *createWebAssemblyArgumentMove();
FunctionPass *createWebAssemblySetP2AlignOperands();
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
index 3d1022d..8833aee 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
@@ -47,7 +47,7 @@
WebAssemblyDAGToDAGISel() = delete;
WebAssemblyDAGToDAGISel(WebAssemblyTargetMachine &TM,
- CodeGenOpt::Level OptLevel)
+ CodeGenOptLevel OptLevel)
: SelectionDAGISel(ID, TM, OptLevel), Subtarget(nullptr) {}
bool runOnMachineFunction(MachineFunction &MF) override {
@@ -408,6 +408,6 @@
/// This pass converts a legalized DAG into a WebAssembly-specific DAG, ready
/// for instruction scheduling.
FunctionPass *llvm::createWebAssemblyISelDag(WebAssemblyTargetMachine &TM,
- CodeGenOpt::Level OptLevel) {
+ CodeGenOptLevel OptLevel) {
return new WebAssemblyDAGToDAGISel(TM, OptLevel);
}
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
index f8a4b95..10464e8 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
@@ -107,7 +107,7 @@
WebAssemblyTargetMachine::WebAssemblyTargetMachine(
const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
const TargetOptions &Options, std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(
T,
TT.isArch64Bit()
@@ -426,7 +426,7 @@
addPass(createWebAssemblyFixFunctionBitcasts());
// Optimize "returned" function attributes.
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOptLevel::None)
addPass(createWebAssemblyOptimizeReturned());
basicCheckForEHAndSjLj(TM);
@@ -503,7 +503,7 @@
// usually not used for production builds.
// TODO Investigate why RegisterCoalesce degrades debug info quality and fix
// it properly
- if (getOptLevel() == CodeGenOpt::Less)
+ if (getOptLevel() == CodeGenOptLevel::Less)
disablePass(&RegisterCoalescerID);
TargetPassConfig::addOptimizedRegAlloc();
}
@@ -550,7 +550,7 @@
addPass(createWebAssemblyReplacePhysRegs());
// Preparations and optimizations related to register stackification.
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOptLevel::None) {
// Depend on LiveIntervals and perform some optimizations on it.
addPass(createWebAssemblyOptimizeLiveIntervals());
@@ -585,7 +585,7 @@
addPass(createWebAssemblyLowerBrUnless());
// Perform the very last peephole optimizations on the code.
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOptLevel::None)
addPass(createWebAssemblyPeephole());
// Create a mapping from LLVM CodeGen virtual registers to wasm registers.
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
index 04bf2de..2e8cd43 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
@@ -30,7 +30,7 @@
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT);
+ CodeGenOptLevel OL, bool JIT);
~WebAssemblyTargetMachine() override;
diff --git a/llvm/lib/Target/X86/X86.h b/llvm/lib/Target/X86/X86.h
index 76ecc77..3c5ca07 100644
--- a/llvm/lib/Target/X86/X86.h
+++ b/llvm/lib/Target/X86/X86.h
@@ -27,8 +27,7 @@
/// This pass converts a legalized DAG into a X86-specific DAG, ready for
/// instruction scheduling.
-FunctionPass *createX86ISelDag(X86TargetMachine &TM,
- CodeGenOpt::Level OptLevel);
+FunctionPass *createX86ISelDag(X86TargetMachine &TM, CodeGenOptLevel OptLevel);
/// This pass initializes a global base register for PIC on x86-32.
FunctionPass *createX86GlobalBaseRegPass();
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index fed2611..fa58748 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -173,7 +173,7 @@
X86DAGToDAGISel() = delete;
- explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
+ explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOptLevel OptLevel)
: SelectionDAGISel(ID, tm, OptLevel), Subtarget(nullptr),
OptForMinSize(false), IndirectTlsSegRefs(false) {}
@@ -624,7 +624,8 @@
bool
X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
- if (OptLevel == CodeGenOpt::None) return false;
+ if (OptLevel == CodeGenOptLevel::None)
+ return false;
if (!N.hasOneUse())
return false;
@@ -1242,7 +1243,7 @@
}
}
- if (OptLevel != CodeGenOpt::None &&
+ if (OptLevel != CodeGenOptLevel::None &&
// Only do this when the target can fold the load into the call or
// jmp.
!Subtarget->useIndirectThunkCalls() &&
@@ -1481,7 +1482,7 @@
void X86DAGToDAGISel::PostprocessISelDAG() {
// Skip peepholes at -O0.
- if (TM.getOptLevel() == CodeGenOpt::None)
+ if (TM.getOptLevel() == CodeGenOptLevel::None)
return;
SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_end();
@@ -6351,6 +6352,6 @@
/// This pass converts a legalized DAG into a X86-specific DAG,
/// ready for instruction scheduling.
FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
- CodeGenOpt::Level OptLevel) {
+ CodeGenOptLevel OptLevel) {
return new X86DAGToDAGISel(TM, OptLevel);
}
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 008e34a..5c0c3af 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -116,7 +116,7 @@
setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
// Bypass expensive divides and use cheaper ones.
- if (TM.getOptLevel() >= CodeGenOpt::Default) {
+ if (TM.getOptLevel() >= CodeGenOptLevel::Default) {
if (Subtarget.hasSlowDivide32())
addBypassSlowDiv(32, 8);
if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit())
@@ -21513,7 +21513,7 @@
DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
"Unexpected type in LowerFABSorFNEG");
- // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
+ // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOptLevel to
// decide if we should generate a 16-byte constant mask when we only need 4 or
// 8 bytes for the scalar case.
diff --git a/llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp b/llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp
index 102a8ce..7163760 100644
--- a/llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp
+++ b/llvm/lib/Target/X86/X86LowerAMXIntrinsics.cpp
@@ -646,7 +646,7 @@
return false;
TargetMachine *TM = &getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
if (!F.hasFnAttribute(Attribute::OptimizeNone) &&
- TM->getOptLevel() != CodeGenOpt::None)
+ TM->getOptLevel() != CodeGenOptLevel::None)
return false;
auto *DTWP = getAnalysisIfAvailable<DominatorTreeWrapperPass>();
diff --git a/llvm/lib/Target/X86/X86LowerAMXType.cpp b/llvm/lib/Target/X86/X86LowerAMXType.cpp
index d20d5fe..cea8b80d 100644
--- a/llvm/lib/Target/X86/X86LowerAMXType.cpp
+++ b/llvm/lib/Target/X86/X86LowerAMXType.cpp
@@ -1247,8 +1247,8 @@
// Prepare for fast register allocation at O0.
// Todo: May better check the volatile model of AMX code, not just
- // by checking Attribute::OptimizeNone and CodeGenOpt::None.
- if (TM->getOptLevel() == CodeGenOpt::None) {
+ // by checking Attribute::OptimizeNone and CodeGenOptLevel::None.
+ if (TM->getOptLevel() == CodeGenOptLevel::None) {
// If Front End not use O0 but the Mid/Back end use O0, (e.g.
// "Clang -O2 -S -emit-llvm t.c" + "llc t.ll") we should make
// sure the amx data is volatile, that is nessary for AMX fast
diff --git a/llvm/lib/Target/X86/X86PreAMXConfig.cpp b/llvm/lib/Target/X86/X86PreAMXConfig.cpp
index c9c59af..7872a64 100644
--- a/llvm/lib/Target/X86/X86PreAMXConfig.cpp
+++ b/llvm/lib/Target/X86/X86PreAMXConfig.cpp
@@ -383,7 +383,7 @@
bool C = false;
// Prepare for fast register allocation at O0.
- if (TM->getOptLevel() == CodeGenOpt::None) {
+ if (TM->getOptLevel() == CodeGenOptLevel::None) {
// We pre-config each key AMX intrinsic at O0.
// In theory, one tile config can cover several AMX intrinsics, but
diff --git a/llvm/lib/Target/X86/X86SpeculativeExecutionSideEffectSuppression.cpp b/llvm/lib/Target/X86/X86SpeculativeExecutionSideEffectSuppression.cpp
index d578711..5d93a37 100644
--- a/llvm/lib/Target/X86/X86SpeculativeExecutionSideEffectSuppression.cpp
+++ b/llvm/lib/Target/X86/X86SpeculativeExecutionSideEffectSuppression.cpp
@@ -95,7 +95,7 @@
// user explicitly passed an SESES flag, or whether the SESES target feature
// was set.
if (!EnableSpeculativeExecutionSideEffectSuppression &&
- !(Subtarget.useLVILoadHardening() && OptLevel == CodeGenOpt::None) &&
+ !(Subtarget.useLVILoadHardening() && OptLevel == CodeGenOptLevel::None) &&
!Subtarget.useSpeculativeExecutionSideEffectSuppression())
return false;
diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp
index 14f37e6..c0d3b8a 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.cpp
+++ b/llvm/lib/Target/X86/X86TargetMachine.cpp
@@ -224,7 +224,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(
T, computeDataLayout(TT), TT, CPU, FS, Options,
getEffectiveRelocModel(TT, JIT, RM),
@@ -443,7 +443,7 @@
TargetPassConfig::addIRPasses();
- if (TM->getOptLevel() != CodeGenOpt::None) {
+ if (TM->getOptLevel() != CodeGenOptLevel::None) {
addPass(createInterleavedAccessPass());
addPass(createX86PartialReductionPass());
}
@@ -473,7 +473,7 @@
// For ELF, cleanup any local-dynamic TLS accesses.
if (TM->getTargetTriple().isOSBinFormatELF() &&
- getOptLevel() != CodeGenOpt::None)
+ getOptLevel() != CodeGenOptLevel::None)
addPass(createCleanupLocalDynamicTLSPass());
addPass(createX86GlobalBaseRegPass());
@@ -518,7 +518,7 @@
}
void X86PassConfig::addPreRegAlloc() {
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOptLevel::None) {
addPass(&LiveRangeShrinkID);
addPass(createX86FixupSetCC());
addPass(createX86OptimizeLEAs());
@@ -530,7 +530,7 @@
addPass(createX86FlagsCopyLoweringPass());
addPass(createX86DynAllocaExpander());
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOptLevel::None)
addPass(createX86PreTileConfigPass());
else
addPass(createX86FastPreTileConfigPass());
@@ -548,7 +548,7 @@
// to using the Speculative Execution Side Effect Suppression pass for
// mitigation. This is to prevent slow downs due to
// analyses needed by the LVIHardening pass when compiling at -O0.
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOptLevel::None)
addPass(createX86LoadValueInjectionLoadHardeningPass());
}
@@ -558,7 +558,7 @@
}
void X86PassConfig::addPreEmitPass() {
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOptLevel::None) {
addPass(new X86ExecutionDomainFix());
addPass(createBreakFalseDeps());
}
@@ -567,7 +567,7 @@
addPass(createX86IssueVZeroUpperPass());
- if (getOptLevel() != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOptLevel::None) {
addPass(createX86FixupBWInsts());
addPass(createX86PadShortFunctions());
addPass(createX86FixupLEAs());
diff --git a/llvm/lib/Target/X86/X86TargetMachine.h b/llvm/lib/Target/X86/X86TargetMachine.h
index 5ea51e2..4836be4d 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.h
+++ b/llvm/lib/Target/X86/X86TargetMachine.h
@@ -35,7 +35,7 @@
X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
~X86TargetMachine() override;
diff --git a/llvm/lib/Target/XCore/XCore.h b/llvm/lib/Target/XCore/XCore.h
index aae1e34..f019fa4 100644
--- a/llvm/lib/Target/XCore/XCore.h
+++ b/llvm/lib/Target/XCore/XCore.h
@@ -29,7 +29,7 @@
FunctionPass *createXCoreFrameToArgsOffsetEliminationPass();
FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM,
- CodeGenOpt::Level OptLevel);
+ CodeGenOptLevel OptLevel);
ModulePass *createXCoreLowerThreadLocalPass();
void initializeXCoreDAGToDAGISelPass(PassRegistry &);
diff --git a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
index 54ee759..1288597 100644
--- a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
+++ b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
@@ -45,8 +45,8 @@
XCoreDAGToDAGISel() = delete;
- XCoreDAGToDAGISel(XCoreTargetMachine &TM, CodeGenOpt::Level OptLevel)
- : SelectionDAGISel(ID, TM, OptLevel) {}
+ XCoreDAGToDAGISel(XCoreTargetMachine &TM, CodeGenOptLevel OptLevel)
+ : SelectionDAGISel(ID, TM, OptLevel) {}
void Select(SDNode *N) override;
bool tryBRIND(SDNode *N);
@@ -88,8 +88,8 @@
/// XCore-specific DAG, ready for instruction scheduling.
///
FunctionPass *llvm::createXCoreISelDag(XCoreTargetMachine &TM,
- CodeGenOpt::Level OptLevel) {
- return new XCoreDAGToDAGISel(TM, OptLevel);
+ CodeGenOptLevel OptLevel) {
+ return new XCoreDAGToDAGISel(TM, OptLevel);
}
bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Addr, SDValue &Base,
diff --git a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp
index 410c854..345a836 100644
--- a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp
+++ b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp
@@ -47,7 +47,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
: LLVMTargetMachine(
T, "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32",
TT, CPU, FS, Options, getEffectiveRelocModel(RM),
diff --git a/llvm/lib/Target/XCore/XCoreTargetMachine.h b/llvm/lib/Target/XCore/XCoreTargetMachine.h
index b45287d..2327693 100644
--- a/llvm/lib/Target/XCore/XCoreTargetMachine.h
+++ b/llvm/lib/Target/XCore/XCoreTargetMachine.h
@@ -31,7 +31,7 @@
XCoreTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
~XCoreTargetMachine() override;
diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
index 561ff4f..c891ecd 100644
--- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
@@ -47,7 +47,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT,
+ CodeGenOptLevel OL, bool JIT,
bool IsLittle)
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, IsLittle), TT,
CPU, FS, Options, getEffectiveRelocModel(JIT, RM),
@@ -61,7 +61,7 @@
const TargetOptions &Options,
std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM,
- CodeGenOpt::Level OL, bool JIT)
+ CodeGenOptLevel OL, bool JIT)
: XtensaTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
TargetPassConfig *XtensaTargetMachine::createPassConfig(PassManagerBase &PM) {
diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.h b/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
index 866ccdc..dd76f45 100644
--- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
+++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
@@ -27,13 +27,13 @@
XtensaTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT, bool isLittle);
XtensaTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
std::optional<Reloc::Model> RM,
- std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
+ std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
