commit | 096ab51de03437e38f97a48b8f2d453fb903414a | [log] [tgz] |
---|---|---|
author | Jason Molenda <jmolenda@apple.com> | Wed Apr 23 22:10:15 2025 -0700 |
committer | GitHub <noreply@github.com> | Wed Apr 23 22:10:15 2025 -0700 |
tree | 4a4f245a68bdcbae4741acc7ff2a7ef23652820a | |
parent | 31c7997a4acb838c94d5ab40baaf154556532ad9 [diff] |
[lldb][MachO] MachO corefile support for riscv32 binaries (#137092) Add support for reading a macho corefile with CPU_TYPE_RISCV and the riscv32 general purpose register file. I added code for the floating point and exception registers too, but haven't exercised this. If we start putting the full CSR register bank in a riscv corefile, it'll be in separate 4k byte chunks, but I don't have a corefile to test against that so I haven't written the code to read it. The RegisterContextDarwin_riscv32 is copied & in the style of the other RegisterContextDarwin classes; it's not the first choice I would make for representing this, but it wasn't worth changing for this cputype. rdar://145014653
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