)]}'
{
  "commit": "08de4fd0d4c3d1e40a151a5c8bed6fd8aee4752b",
  "tree": "7167fc4798ed45f02c8f0057a0c8184a592d45a9",
  "parents": [
    "6bb20438598bfced09b1afbb76e551fbb955060d"
  ],
  "author": {
    "name": "Craig Topper",
    "email": "craig.topper@sifive.com",
    "time": "Thu Jan 15 09:35:02 2026 -0800"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Thu Jan 15 09:35:02 2026 -0800"
  },
  "message": "[SelectionDAG] Move HwMode expansion from tablegen to SelectionISel. (#174471)\n\nThe way HwMode is currently implemented, tablegen duplicates each\npattern that is dependent on hardware mode. The HwMode predicate is\nadded as a pattern predicate on the duplicated pattern.\n    \nRISC-V uses HwMode on the GPR register class which means almost every\nisel pattern is affected by HwMode. This results in the isel table\nbeing nearly twice the size it would be if we only had a single GPR\nsize.\n\nThis patch proposes to do the expansion at instruction selection time\ninstead. To accomplish this new opcodes like OPC_CheckTypeByHwMode\nare added to the isel table. The unique combinations of types and HwMode\nare converted to an index that is the payload for the new opcodes.\nTableGen emits a new virtual function getValueTypeByHwMode that uses\nthis index and the current HwMode to look up the type.\n\nThis reduces the size of the isel table on RISC-V from ~2.38 million\nbytes to ~1.38 million bytes.\n\nI did not add an OPC_SwitchTypeByHwMode opcode yet. If the VT requires a\nhardware mode, we emit an OPC_Scope+OPC_CheckTypeByHwMode instead. I\nexpect adding an OPC_SwitchTypeByHwMode could further reduce the table\nsize. I will investigate this as a follow up.\n    \nMany of the matcher classes in tablegen now use ValueTypeByHwMode\ninsteadof MVT. This may have an impact on the memory usage and runtime of\ntablegen. We can mitigate some of this by splitting the matchers into MVT and\nValueTypeByHwMode versions. We can also explore alternate data\nstructures for ValueTypeByHwMode instead of a std::map. Maybe a sorted vector.\n\nA similar change can be made to GlobalISel as a follow up.",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1a5430826405682b4941a09fa67e852cdba65575",
      "old_mode": 33188,
      "old_path": "llvm/include/llvm/CodeGen/SelectionDAGISel.h",
      "new_id": "8a9e98330f895d77dfe38bdef7ec16a85596a967",
      "new_mode": 33188,
      "new_path": "llvm/include/llvm/CodeGen/SelectionDAGISel.h"
    },
    {
      "type": "modify",
      "old_id": "e092061fb5e049c22816cfab0f12536748ab1835",
      "old_mode": 33188,
      "old_path": "llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp",
      "new_id": "2aa775115811ad1de68a8166abae1d054b94325c",
      "new_mode": 33188,
      "new_path": "llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp"
    },
    {
      "type": "modify",
      "old_id": "2e5e6d08ddae616d5b8e383718682a637300705a",
      "old_mode": 33188,
      "old_path": "llvm/test/TableGen/RegClassByHwMode.td",
      "new_id": "508b098c9f44ea442ca1ad36b9036d0f41f55b87",
      "new_mode": 33188,
      "new_path": "llvm/test/TableGen/RegClassByHwMode.td"
    },
    {
      "type": "modify",
      "old_id": "c3e07979467de026cb252ac85547dee6cb7c96a0",
      "old_mode": 33188,
      "old_path": "llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp",
      "new_id": "3ed5fe5d806ae61908900fd178c6ad7f6281bca4",
      "new_mode": 33188,
      "new_path": "llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp"
    },
    {
      "type": "modify",
      "old_id": "220fa43bf503791a768f912ba59940b3880958b1",
      "old_mode": 33188,
      "old_path": "llvm/utils/TableGen/Common/CodeGenDAGPatterns.h",
      "new_id": "7d93e9ce126d5b9eb8724a2a9469672b27105787",
      "new_mode": 33188,
      "new_path": "llvm/utils/TableGen/Common/CodeGenDAGPatterns.h"
    },
    {
      "type": "modify",
      "old_id": "65d2835018f1e571595b66769194f517bb6d80ee",
      "old_mode": 33188,
      "old_path": "llvm/utils/TableGen/DAGISelEmitter.cpp",
      "new_id": "dc66967584f7160839bd3c5cbeacc290f03010c6",
      "new_mode": 33188,
      "new_path": "llvm/utils/TableGen/DAGISelEmitter.cpp"
    },
    {
      "type": "modify",
      "old_id": "3ec20e318f680eacdb4ac30e9049079fbd11458a",
      "old_mode": 33188,
      "old_path": "llvm/utils/TableGen/DAGISelMatcher.cpp",
      "new_id": "a68ebf3551cf38121065c23209e1051186c3dd48",
      "new_mode": 33188,
      "new_path": "llvm/utils/TableGen/DAGISelMatcher.cpp"
    },
    {
      "type": "modify",
      "old_id": "192d5c47d3489ea00a53e7959d01e9d7cb00ee60",
      "old_mode": 33188,
      "old_path": "llvm/utils/TableGen/DAGISelMatcher.h",
      "new_id": "f2a75147c2acad52bf18713dbcfe1965c0b84c7e",
      "new_mode": 33188,
      "new_path": "llvm/utils/TableGen/DAGISelMatcher.h"
    },
    {
      "type": "modify",
      "old_id": "3d573483afebf9cce009e8960931058a696e1008",
      "old_mode": 33188,
      "old_path": "llvm/utils/TableGen/DAGISelMatcherEmitter.cpp",
      "new_id": "95338b906568a8d838281d8c27d9a51d5ba210d5",
      "new_mode": 33188,
      "new_path": "llvm/utils/TableGen/DAGISelMatcherEmitter.cpp"
    },
    {
      "type": "modify",
      "old_id": "fc0564b18a35635e47bddafe0d7b39058df27518",
      "old_mode": 33188,
      "old_path": "llvm/utils/TableGen/DAGISelMatcherGen.cpp",
      "new_id": "e8f146264b1ec94143a136a5a29b237db10fe4fd",
      "new_mode": 33188,
      "new_path": "llvm/utils/TableGen/DAGISelMatcherGen.cpp"
    },
    {
      "type": "modify",
      "old_id": "222b73ddd8befed129b7388d54e9585dc8230034",
      "old_mode": 33188,
      "old_path": "llvm/utils/TableGen/DAGISelMatcherOpt.cpp",
      "new_id": "9a40ecd30edff17628717ccd06d6d99c901e3f15",
      "new_mode": 33188,
      "new_path": "llvm/utils/TableGen/DAGISelMatcherOpt.cpp"
    }
  ]
}
