[RISCV] Add codegen support for RV64A
In order to support codegen RV64A, this patch:
* Introduces masked atomics intrinsics for atomicrmw operations and cmpxchg
that use the i64 type. These are ultimately lowered to masked operations
using lr.w/sc.w, but we need to use these alternate intrinsics for RV64
because i32 is not legal
* Modifies RISCVExpandPseudoInsts.cpp to handle PseudoAtomicLoadNand64 and
PseudoCmpXchg64
* Modifies the AtomicExpandPass hooks in RISCVTargetLowering to sext/trunc as
needed for RV64 and to select the i64 intrinsic IDs when necessary
* Adds appropriate patterns to RISCVInstrInfoA.td
* Updates test/CodeGen/RISCV/atomic-*.ll to show RV64A support
This ends up being a fairly mechanical change, as the logic for RV32A is
effectively reused.
Differential Revision: https://reviews.llvm.org/D53233
llvm-svn: 351422
diff --git a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
index 19b85b6..8818645 100644
--- a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
@@ -5,6 +5,8 @@
; RUN: | FileCheck -check-prefix=RV32IA %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
+; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64IA %s
define void @cmpxchg_i8_monotonic_monotonic(i8* %ptr, i8 %cmp, i8 %val) {
; RV32I-LABEL: cmpxchg_i8_monotonic_monotonic:
@@ -56,6 +58,30 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i8_monotonic_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a3, a0, 3
+; RV64IA-NEXT: slli a3, a3, 3
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a4, a4, a3
+; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: sllw a2, a2, a3
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a3
+; RV64IA-NEXT: andi a0, a0, -4
+; RV64IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a3, (a0)
+; RV64IA-NEXT: and a5, a3, a4
+; RV64IA-NEXT: bne a5, a1, .LBB0_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB0_1 Depth=1
+; RV64IA-NEXT: xor a5, a3, a2
+; RV64IA-NEXT: and a5, a5, a4
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: sc.w a5, a5, (a0)
+; RV64IA-NEXT: bnez a5, .LBB0_1
+; RV64IA-NEXT: .LBB0_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic
ret void
}
@@ -110,6 +136,30 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i8_acquire_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a3, a0, 3
+; RV64IA-NEXT: slli a3, a3, 3
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a4, a4, a3
+; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: sllw a2, a2, a3
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a3
+; RV64IA-NEXT: andi a0, a0, -4
+; RV64IA-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aq a3, (a0)
+; RV64IA-NEXT: and a5, a3, a4
+; RV64IA-NEXT: bne a5, a1, .LBB1_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB1_1 Depth=1
+; RV64IA-NEXT: xor a5, a3, a2
+; RV64IA-NEXT: and a5, a5, a4
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: sc.w a5, a5, (a0)
+; RV64IA-NEXT: bnez a5, .LBB1_1
+; RV64IA-NEXT: .LBB1_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire monotonic
ret void
}
@@ -164,6 +214,30 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i8_acquire_acquire:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a3, a0, 3
+; RV64IA-NEXT: slli a3, a3, 3
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a4, a4, a3
+; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: sllw a2, a2, a3
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a3
+; RV64IA-NEXT: andi a0, a0, -4
+; RV64IA-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aq a3, (a0)
+; RV64IA-NEXT: and a5, a3, a4
+; RV64IA-NEXT: bne a5, a1, .LBB2_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB2_1 Depth=1
+; RV64IA-NEXT: xor a5, a3, a2
+; RV64IA-NEXT: and a5, a5, a4
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: sc.w a5, a5, (a0)
+; RV64IA-NEXT: bnez a5, .LBB2_1
+; RV64IA-NEXT: .LBB2_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire acquire
ret void
}
@@ -218,6 +292,30 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i8_release_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a3, a0, 3
+; RV64IA-NEXT: slli a3, a3, 3
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a4, a4, a3
+; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: sllw a2, a2, a3
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a3
+; RV64IA-NEXT: andi a0, a0, -4
+; RV64IA-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a3, (a0)
+; RV64IA-NEXT: and a5, a3, a4
+; RV64IA-NEXT: bne a5, a1, .LBB3_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB3_1 Depth=1
+; RV64IA-NEXT: xor a5, a3, a2
+; RV64IA-NEXT: and a5, a5, a4
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT: bnez a5, .LBB3_1
+; RV64IA-NEXT: .LBB3_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release monotonic
ret void
}
@@ -272,6 +370,30 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i8_release_acquire:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a3, a0, 3
+; RV64IA-NEXT: slli a3, a3, 3
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a4, a4, a3
+; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: sllw a2, a2, a3
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a3
+; RV64IA-NEXT: andi a0, a0, -4
+; RV64IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a3, (a0)
+; RV64IA-NEXT: and a5, a3, a4
+; RV64IA-NEXT: bne a5, a1, .LBB4_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB4_1 Depth=1
+; RV64IA-NEXT: xor a5, a3, a2
+; RV64IA-NEXT: and a5, a5, a4
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT: bnez a5, .LBB4_1
+; RV64IA-NEXT: .LBB4_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release acquire
ret void
}
@@ -326,6 +448,30 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i8_acq_rel_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a3, a0, 3
+; RV64IA-NEXT: slli a3, a3, 3
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a4, a4, a3
+; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: sllw a2, a2, a3
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a3
+; RV64IA-NEXT: andi a0, a0, -4
+; RV64IA-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aq a3, (a0)
+; RV64IA-NEXT: and a5, a3, a4
+; RV64IA-NEXT: bne a5, a1, .LBB5_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB5_1 Depth=1
+; RV64IA-NEXT: xor a5, a3, a2
+; RV64IA-NEXT: and a5, a5, a4
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT: bnez a5, .LBB5_1
+; RV64IA-NEXT: .LBB5_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel monotonic
ret void
}
@@ -380,6 +526,30 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i8_acq_rel_acquire:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a3, a0, 3
+; RV64IA-NEXT: slli a3, a3, 3
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a4, a4, a3
+; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: sllw a2, a2, a3
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a3
+; RV64IA-NEXT: andi a0, a0, -4
+; RV64IA-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aq a3, (a0)
+; RV64IA-NEXT: and a5, a3, a4
+; RV64IA-NEXT: bne a5, a1, .LBB6_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB6_1 Depth=1
+; RV64IA-NEXT: xor a5, a3, a2
+; RV64IA-NEXT: and a5, a5, a4
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT: bnez a5, .LBB6_1
+; RV64IA-NEXT: .LBB6_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel acquire
ret void
}
@@ -434,6 +604,30 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i8_seq_cst_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a3, a0, 3
+; RV64IA-NEXT: slli a3, a3, 3
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a4, a4, a3
+; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: sllw a2, a2, a3
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a3
+; RV64IA-NEXT: andi a0, a0, -4
+; RV64IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a3, (a0)
+; RV64IA-NEXT: and a5, a3, a4
+; RV64IA-NEXT: bne a5, a1, .LBB7_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB7_1 Depth=1
+; RV64IA-NEXT: xor a5, a3, a2
+; RV64IA-NEXT: and a5, a5, a4
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0)
+; RV64IA-NEXT: bnez a5, .LBB7_1
+; RV64IA-NEXT: .LBB7_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst monotonic
ret void
}
@@ -488,6 +682,30 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i8_seq_cst_acquire:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a3, a0, 3
+; RV64IA-NEXT: slli a3, a3, 3
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a4, a4, a3
+; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: sllw a2, a2, a3
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a3
+; RV64IA-NEXT: andi a0, a0, -4
+; RV64IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a3, (a0)
+; RV64IA-NEXT: and a5, a3, a4
+; RV64IA-NEXT: bne a5, a1, .LBB8_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB8_1 Depth=1
+; RV64IA-NEXT: xor a5, a3, a2
+; RV64IA-NEXT: and a5, a5, a4
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0)
+; RV64IA-NEXT: bnez a5, .LBB8_1
+; RV64IA-NEXT: .LBB8_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst acquire
ret void
}
@@ -542,6 +760,30 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i8_seq_cst_seq_cst:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a3, a0, 3
+; RV64IA-NEXT: slli a3, a3, 3
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a4, a4, a3
+; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: sllw a2, a2, a3
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a3
+; RV64IA-NEXT: andi a0, a0, -4
+; RV64IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a3, (a0)
+; RV64IA-NEXT: and a5, a3, a4
+; RV64IA-NEXT: bne a5, a1, .LBB9_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB9_1 Depth=1
+; RV64IA-NEXT: xor a5, a3, a2
+; RV64IA-NEXT: and a5, a5, a4
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0)
+; RV64IA-NEXT: bnez a5, .LBB9_1
+; RV64IA-NEXT: .LBB9_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst seq_cst
ret void
}
@@ -597,6 +839,31 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i16_monotonic_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: lui a3, 16
+; RV64IA-NEXT: addiw a3, a3, -1
+; RV64IA-NEXT: and a1, a1, a3
+; RV64IA-NEXT: and a2, a2, a3
+; RV64IA-NEXT: andi a4, a0, 3
+; RV64IA-NEXT: slli a4, a4, 3
+; RV64IA-NEXT: sllw a3, a3, a4
+; RV64IA-NEXT: sllw a2, a2, a4
+; RV64IA-NEXT: sllw a1, a1, a4
+; RV64IA-NEXT: andi a0, a0, -4
+; RV64IA-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a4, (a0)
+; RV64IA-NEXT: and a5, a4, a3
+; RV64IA-NEXT: bne a5, a1, .LBB10_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB10_1 Depth=1
+; RV64IA-NEXT: xor a5, a4, a2
+; RV64IA-NEXT: and a5, a5, a3
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: sc.w a5, a5, (a0)
+; RV64IA-NEXT: bnez a5, .LBB10_1
+; RV64IA-NEXT: .LBB10_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val monotonic monotonic
ret void
}
@@ -652,6 +919,31 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i16_acquire_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: lui a3, 16
+; RV64IA-NEXT: addiw a3, a3, -1
+; RV64IA-NEXT: and a1, a1, a3
+; RV64IA-NEXT: and a2, a2, a3
+; RV64IA-NEXT: andi a4, a0, 3
+; RV64IA-NEXT: slli a4, a4, 3
+; RV64IA-NEXT: sllw a3, a3, a4
+; RV64IA-NEXT: sllw a2, a2, a4
+; RV64IA-NEXT: sllw a1, a1, a4
+; RV64IA-NEXT: andi a0, a0, -4
+; RV64IA-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aq a4, (a0)
+; RV64IA-NEXT: and a5, a4, a3
+; RV64IA-NEXT: bne a5, a1, .LBB11_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB11_1 Depth=1
+; RV64IA-NEXT: xor a5, a4, a2
+; RV64IA-NEXT: and a5, a5, a3
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: sc.w a5, a5, (a0)
+; RV64IA-NEXT: bnez a5, .LBB11_1
+; RV64IA-NEXT: .LBB11_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire monotonic
ret void
}
@@ -707,6 +999,31 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i16_acquire_acquire:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: lui a3, 16
+; RV64IA-NEXT: addiw a3, a3, -1
+; RV64IA-NEXT: and a1, a1, a3
+; RV64IA-NEXT: and a2, a2, a3
+; RV64IA-NEXT: andi a4, a0, 3
+; RV64IA-NEXT: slli a4, a4, 3
+; RV64IA-NEXT: sllw a3, a3, a4
+; RV64IA-NEXT: sllw a2, a2, a4
+; RV64IA-NEXT: sllw a1, a1, a4
+; RV64IA-NEXT: andi a0, a0, -4
+; RV64IA-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aq a4, (a0)
+; RV64IA-NEXT: and a5, a4, a3
+; RV64IA-NEXT: bne a5, a1, .LBB12_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB12_1 Depth=1
+; RV64IA-NEXT: xor a5, a4, a2
+; RV64IA-NEXT: and a5, a5, a3
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: sc.w a5, a5, (a0)
+; RV64IA-NEXT: bnez a5, .LBB12_1
+; RV64IA-NEXT: .LBB12_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire acquire
ret void
}
@@ -762,6 +1079,31 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i16_release_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: lui a3, 16
+; RV64IA-NEXT: addiw a3, a3, -1
+; RV64IA-NEXT: and a1, a1, a3
+; RV64IA-NEXT: and a2, a2, a3
+; RV64IA-NEXT: andi a4, a0, 3
+; RV64IA-NEXT: slli a4, a4, 3
+; RV64IA-NEXT: sllw a3, a3, a4
+; RV64IA-NEXT: sllw a2, a2, a4
+; RV64IA-NEXT: sllw a1, a1, a4
+; RV64IA-NEXT: andi a0, a0, -4
+; RV64IA-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a4, (a0)
+; RV64IA-NEXT: and a5, a4, a3
+; RV64IA-NEXT: bne a5, a1, .LBB13_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB13_1 Depth=1
+; RV64IA-NEXT: xor a5, a4, a2
+; RV64IA-NEXT: and a5, a5, a3
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT: bnez a5, .LBB13_1
+; RV64IA-NEXT: .LBB13_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release monotonic
ret void
}
@@ -817,6 +1159,31 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i16_release_acquire:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: lui a3, 16
+; RV64IA-NEXT: addiw a3, a3, -1
+; RV64IA-NEXT: and a1, a1, a3
+; RV64IA-NEXT: and a2, a2, a3
+; RV64IA-NEXT: andi a4, a0, 3
+; RV64IA-NEXT: slli a4, a4, 3
+; RV64IA-NEXT: sllw a3, a3, a4
+; RV64IA-NEXT: sllw a2, a2, a4
+; RV64IA-NEXT: sllw a1, a1, a4
+; RV64IA-NEXT: andi a0, a0, -4
+; RV64IA-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a4, (a0)
+; RV64IA-NEXT: and a5, a4, a3
+; RV64IA-NEXT: bne a5, a1, .LBB14_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB14_1 Depth=1
+; RV64IA-NEXT: xor a5, a4, a2
+; RV64IA-NEXT: and a5, a5, a3
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT: bnez a5, .LBB14_1
+; RV64IA-NEXT: .LBB14_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release acquire
ret void
}
@@ -872,6 +1239,31 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i16_acq_rel_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: lui a3, 16
+; RV64IA-NEXT: addiw a3, a3, -1
+; RV64IA-NEXT: and a1, a1, a3
+; RV64IA-NEXT: and a2, a2, a3
+; RV64IA-NEXT: andi a4, a0, 3
+; RV64IA-NEXT: slli a4, a4, 3
+; RV64IA-NEXT: sllw a3, a3, a4
+; RV64IA-NEXT: sllw a2, a2, a4
+; RV64IA-NEXT: sllw a1, a1, a4
+; RV64IA-NEXT: andi a0, a0, -4
+; RV64IA-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aq a4, (a0)
+; RV64IA-NEXT: and a5, a4, a3
+; RV64IA-NEXT: bne a5, a1, .LBB15_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB15_1 Depth=1
+; RV64IA-NEXT: xor a5, a4, a2
+; RV64IA-NEXT: and a5, a5, a3
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT: bnez a5, .LBB15_1
+; RV64IA-NEXT: .LBB15_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel monotonic
ret void
}
@@ -927,6 +1319,31 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i16_acq_rel_acquire:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: lui a3, 16
+; RV64IA-NEXT: addiw a3, a3, -1
+; RV64IA-NEXT: and a1, a1, a3
+; RV64IA-NEXT: and a2, a2, a3
+; RV64IA-NEXT: andi a4, a0, 3
+; RV64IA-NEXT: slli a4, a4, 3
+; RV64IA-NEXT: sllw a3, a3, a4
+; RV64IA-NEXT: sllw a2, a2, a4
+; RV64IA-NEXT: sllw a1, a1, a4
+; RV64IA-NEXT: andi a0, a0, -4
+; RV64IA-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aq a4, (a0)
+; RV64IA-NEXT: and a5, a4, a3
+; RV64IA-NEXT: bne a5, a1, .LBB16_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB16_1 Depth=1
+; RV64IA-NEXT: xor a5, a4, a2
+; RV64IA-NEXT: and a5, a5, a3
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT: bnez a5, .LBB16_1
+; RV64IA-NEXT: .LBB16_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel acquire
ret void
}
@@ -982,6 +1399,31 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i16_seq_cst_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: lui a3, 16
+; RV64IA-NEXT: addiw a3, a3, -1
+; RV64IA-NEXT: and a1, a1, a3
+; RV64IA-NEXT: and a2, a2, a3
+; RV64IA-NEXT: andi a4, a0, 3
+; RV64IA-NEXT: slli a4, a4, 3
+; RV64IA-NEXT: sllw a3, a3, a4
+; RV64IA-NEXT: sllw a2, a2, a4
+; RV64IA-NEXT: sllw a1, a1, a4
+; RV64IA-NEXT: andi a0, a0, -4
+; RV64IA-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a4, (a0)
+; RV64IA-NEXT: and a5, a4, a3
+; RV64IA-NEXT: bne a5, a1, .LBB17_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB17_1 Depth=1
+; RV64IA-NEXT: xor a5, a4, a2
+; RV64IA-NEXT: and a5, a5, a3
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0)
+; RV64IA-NEXT: bnez a5, .LBB17_1
+; RV64IA-NEXT: .LBB17_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst monotonic
ret void
}
@@ -1037,6 +1479,31 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i16_seq_cst_acquire:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: lui a3, 16
+; RV64IA-NEXT: addiw a3, a3, -1
+; RV64IA-NEXT: and a1, a1, a3
+; RV64IA-NEXT: and a2, a2, a3
+; RV64IA-NEXT: andi a4, a0, 3
+; RV64IA-NEXT: slli a4, a4, 3
+; RV64IA-NEXT: sllw a3, a3, a4
+; RV64IA-NEXT: sllw a2, a2, a4
+; RV64IA-NEXT: sllw a1, a1, a4
+; RV64IA-NEXT: andi a0, a0, -4
+; RV64IA-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a4, (a0)
+; RV64IA-NEXT: and a5, a4, a3
+; RV64IA-NEXT: bne a5, a1, .LBB18_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB18_1 Depth=1
+; RV64IA-NEXT: xor a5, a4, a2
+; RV64IA-NEXT: and a5, a5, a3
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0)
+; RV64IA-NEXT: bnez a5, .LBB18_1
+; RV64IA-NEXT: .LBB18_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst acquire
ret void
}
@@ -1092,6 +1559,31 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i16_seq_cst_seq_cst:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: lui a3, 16
+; RV64IA-NEXT: addiw a3, a3, -1
+; RV64IA-NEXT: and a1, a1, a3
+; RV64IA-NEXT: and a2, a2, a3
+; RV64IA-NEXT: andi a4, a0, 3
+; RV64IA-NEXT: slli a4, a4, 3
+; RV64IA-NEXT: sllw a3, a3, a4
+; RV64IA-NEXT: sllw a2, a2, a4
+; RV64IA-NEXT: sllw a1, a1, a4
+; RV64IA-NEXT: andi a0, a0, -4
+; RV64IA-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a4, (a0)
+; RV64IA-NEXT: and a5, a4, a3
+; RV64IA-NEXT: bne a5, a1, .LBB19_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB19_1 Depth=1
+; RV64IA-NEXT: xor a5, a4, a2
+; RV64IA-NEXT: and a5, a5, a3
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0)
+; RV64IA-NEXT: bnez a5, .LBB19_1
+; RV64IA-NEXT: .LBB19_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst seq_cst
ret void
}
@@ -1133,6 +1625,17 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i32_monotonic_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a3, (a0)
+; RV64IA-NEXT: bne a3, a1, .LBB20_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB20_1 Depth=1
+; RV64IA-NEXT: sc.w a4, a2, (a0)
+; RV64IA-NEXT: bnez a4, .LBB20_1
+; RV64IA-NEXT: .LBB20_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val monotonic monotonic
ret void
}
@@ -1174,6 +1677,17 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i32_acquire_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aq a3, (a0)
+; RV64IA-NEXT: bne a3, a1, .LBB21_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB21_1 Depth=1
+; RV64IA-NEXT: sc.w a4, a2, (a0)
+; RV64IA-NEXT: bnez a4, .LBB21_1
+; RV64IA-NEXT: .LBB21_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire monotonic
ret void
}
@@ -1215,6 +1729,17 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i32_acquire_acquire:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aq a3, (a0)
+; RV64IA-NEXT: bne a3, a1, .LBB22_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB22_1 Depth=1
+; RV64IA-NEXT: sc.w a4, a2, (a0)
+; RV64IA-NEXT: bnez a4, .LBB22_1
+; RV64IA-NEXT: .LBB22_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire acquire
ret void
}
@@ -1256,6 +1781,17 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i32_release_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a3, (a0)
+; RV64IA-NEXT: bne a3, a1, .LBB23_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB23_1 Depth=1
+; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
+; RV64IA-NEXT: bnez a4, .LBB23_1
+; RV64IA-NEXT: .LBB23_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release monotonic
ret void
}
@@ -1297,6 +1833,17 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i32_release_acquire:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a3, (a0)
+; RV64IA-NEXT: bne a3, a1, .LBB24_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB24_1 Depth=1
+; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
+; RV64IA-NEXT: bnez a4, .LBB24_1
+; RV64IA-NEXT: .LBB24_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release acquire
ret void
}
@@ -1338,6 +1885,17 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i32_acq_rel_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aq a3, (a0)
+; RV64IA-NEXT: bne a3, a1, .LBB25_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB25_1 Depth=1
+; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
+; RV64IA-NEXT: bnez a4, .LBB25_1
+; RV64IA-NEXT: .LBB25_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel monotonic
ret void
}
@@ -1379,6 +1937,17 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i32_acq_rel_acquire:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aq a3, (a0)
+; RV64IA-NEXT: bne a3, a1, .LBB26_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB26_1 Depth=1
+; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
+; RV64IA-NEXT: bnez a4, .LBB26_1
+; RV64IA-NEXT: .LBB26_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel acquire
ret void
}
@@ -1420,6 +1989,17 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i32_seq_cst_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a3, (a0)
+; RV64IA-NEXT: bne a3, a1, .LBB27_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1
+; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0)
+; RV64IA-NEXT: bnez a4, .LBB27_1
+; RV64IA-NEXT: .LBB27_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst monotonic
ret void
}
@@ -1461,6 +2041,17 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i32_seq_cst_acquire:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a3, (a0)
+; RV64IA-NEXT: bne a3, a1, .LBB28_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1
+; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0)
+; RV64IA-NEXT: bnez a4, .LBB28_1
+; RV64IA-NEXT: .LBB28_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst acquire
ret void
}
@@ -1502,6 +2093,17 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a3, (a0)
+; RV64IA-NEXT: bne a3, a1, .LBB29_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1
+; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0)
+; RV64IA-NEXT: bnez a4, .LBB29_1
+; RV64IA-NEXT: .LBB29_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst seq_cst
ret void
}
@@ -1551,6 +2153,17 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i64_monotonic_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.d a3, (a0)
+; RV64IA-NEXT: bne a3, a1, .LBB30_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB30_1 Depth=1
+; RV64IA-NEXT: sc.d a4, a2, (a0)
+; RV64IA-NEXT: bnez a4, .LBB30_1
+; RV64IA-NEXT: .LBB30_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val monotonic monotonic
ret void
}
@@ -1602,6 +2215,17 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i64_acquire_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.d.aq a3, (a0)
+; RV64IA-NEXT: bne a3, a1, .LBB31_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB31_1 Depth=1
+; RV64IA-NEXT: sc.d a4, a2, (a0)
+; RV64IA-NEXT: bnez a4, .LBB31_1
+; RV64IA-NEXT: .LBB31_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire monotonic
ret void
}
@@ -1651,6 +2275,17 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i64_acquire_acquire:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.d.aq a3, (a0)
+; RV64IA-NEXT: bne a3, a1, .LBB32_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB32_1 Depth=1
+; RV64IA-NEXT: sc.d a4, a2, (a0)
+; RV64IA-NEXT: bnez a4, .LBB32_1
+; RV64IA-NEXT: .LBB32_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire acquire
ret void
}
@@ -1702,6 +2337,17 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i64_release_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.d a3, (a0)
+; RV64IA-NEXT: bne a3, a1, .LBB33_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB33_1 Depth=1
+; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
+; RV64IA-NEXT: bnez a4, .LBB33_1
+; RV64IA-NEXT: .LBB33_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release monotonic
ret void
}
@@ -1753,6 +2399,17 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i64_release_acquire:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.d a3, (a0)
+; RV64IA-NEXT: bne a3, a1, .LBB34_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB34_1 Depth=1
+; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
+; RV64IA-NEXT: bnez a4, .LBB34_1
+; RV64IA-NEXT: .LBB34_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release acquire
ret void
}
@@ -1804,6 +2461,17 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i64_acq_rel_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.d.aq a3, (a0)
+; RV64IA-NEXT: bne a3, a1, .LBB35_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB35_1 Depth=1
+; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
+; RV64IA-NEXT: bnez a4, .LBB35_1
+; RV64IA-NEXT: .LBB35_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel monotonic
ret void
}
@@ -1855,6 +2523,17 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i64_acq_rel_acquire:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.d.aq a3, (a0)
+; RV64IA-NEXT: bne a3, a1, .LBB36_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB36_1 Depth=1
+; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
+; RV64IA-NEXT: bnez a4, .LBB36_1
+; RV64IA-NEXT: .LBB36_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel acquire
ret void
}
@@ -1906,6 +2585,17 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i64_seq_cst_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.d.aqrl a3, (a0)
+; RV64IA-NEXT: bne a3, a1, .LBB37_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1
+; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0)
+; RV64IA-NEXT: bnez a4, .LBB37_1
+; RV64IA-NEXT: .LBB37_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst monotonic
ret void
}
@@ -1957,6 +2647,17 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i64_seq_cst_acquire:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.d.aqrl a3, (a0)
+; RV64IA-NEXT: bne a3, a1, .LBB38_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1
+; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0)
+; RV64IA-NEXT: bnez a4, .LBB38_1
+; RV64IA-NEXT: .LBB38_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst acquire
ret void
}
@@ -2006,6 +2707,17 @@
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
+;
+; RV64IA-LABEL: cmpxchg_i64_seq_cst_seq_cst:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.d.aqrl a3, (a0)
+; RV64IA-NEXT: bne a3, a1, .LBB39_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1
+; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0)
+; RV64IA-NEXT: bnez a4, .LBB39_1
+; RV64IA-NEXT: .LBB39_3:
+; RV64IA-NEXT: ret
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst seq_cst
ret void
}
