| commit | 02ed65912ea36ddbb280c959eebb5df129fa3dfa | [log] [tgz] |
|---|---|---|
| author | Jay Foad <jay.foad@amd.com> | Mon Mar 24 17:11:39 2025 +0000 |
| committer | GitHub <noreply@github.com> | Mon Mar 24 17:11:39 2025 +0000 |
| tree | fefe1b5fc0f645bb98b708d4ab5810c9a72e7355 | |
| parent | 34fa037c4fd7f38faada5beedc63ad234e904247 [diff] |
[AMDGPU] 4-align TTMP triples (#132759) Follow up to e4284a7c70cd "[AMDGPU] 4-align SGPR triples". Previously TTMP triples like ttmp[3:5] were aligned on a 3-TTMP boundary which has no basis in hardware. Aligning them on a 4-TTMP boundary matches what we do for SGPRs, which reduces the number of extra register classes synthesized by TableGen, bringing the total number down from 653 to 615.
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