[VPlan] Plumb scalable register size through narrowInterleaveGroups (#167505) On RISC-V narrowInterleaveGroups doesn't kick in because the wrong VectorRegWidth is passed to isConsecutiveInterleaveGroup. narrowInterleaveGroups is always passed the RGK_FixedWidthVector register size, but on RISC-V the RGK_ScalableVector size is twice as large because we want to use LMUL 2. This causes the `GroupSize == VectorRegWidth` check to fail. This fixes it by using the scalable register size whenever the VF is scalable and plumbing it through as a potentially scalable TypeSize. Note that this only makes a difference when tail folding is disabled, as narrowInterleaveGroups can't handle EVL based IVs yet.
Welcome to the LLVM project!
This repository contains the source code for LLVM, a toolkit for the construction of highly optimized compilers, optimizers, and run-time environments.
The LLVM project has multiple components. The core of the project is itself called “LLVM”. This contains all of the tools, libraries, and header files needed to process intermediate representations and convert them into object files. Tools include an assembler, disassembler, bitcode analyzer, and bitcode optimizer.
C-like languages use the Clang frontend. This component compiles C, C++, Objective-C, and Objective-C++ code into LLVM bitcode -- and from there into object files, using LLVM.
Other components include: the libc++ C++ standard library, the LLD linker, and more.
Consult the Getting Started with LLVM page for information on building and running LLVM.
For information on how to contribute to the LLVM project, please take a look at the Contributing to LLVM guide.
Join the LLVM Discourse forums, Discord chat, LLVM Office Hours or Regular sync-ups.
The LLVM project has adopted a code of conduct for participants to all modes of communication within the project.