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llvm / llvm-project / 0165f8817cbda4dc6a83db0d2994f7ece12726ff
commit0165f8817cbda4dc6a83db0d2994f7ece12726ff[log] [tgz]
authorMin-Yih Hsu <min.hsu@sifive.com>Thu Nov 21 10:59:46 2024 -0800
committerGitHub <noreply@github.com>Thu Nov 21 10:59:46 2024 -0800
treeac2f18da7d40aea21679bc0c9949e35506c26cef
parent040f1c78117f9ec90d951f7560198ec9b2fcaf65 [diff]
[RISCV] Fix the worst case for VSHA2MS in SiFive P400/P600 scheduling models (#116893)

For each RVV instruction we should have a single WriteRes assignment to
the worst case scheduling class. This assignment is usually equal to
that of the largest LMUL + smallest SEW. My #114317 accidentally made
two of these assignments on `WriteVSHA2MSV_WorstCase`. This won't affect
our MachineScheduler nor most of our llvm-mca use cases (assuming you
populate the correct LMUL and SEW), yet it's not ideal either.

This patch fixes this issue by assigning the correct numbers and
resource mapping to `WriteVSHA2MSV_WorstCase`, which is equal to that of
largest LMUL + _largest_ SEW (Zvknh's scheduling properties are
special). I also added a MCA test to make sure we always pick up the
correct worst case numbers for P600's scheduling model.

Original issue was reported by @reidtatge
3 files changed
tree: ac2f18da7d40aea21679bc0c9949e35506c26cef
  1. .ci/
  2. .github/
  3. bolt/
  4. clang/
  5. clang-tools-extra/
  6. cmake/
  7. compiler-rt/
  8. cross-project-tests/
  9. flang/
  10. libc/
  11. libclc/
  12. libcxx/
  13. libcxxabi/
  14. libunwind/
  15. lld/
  16. lldb/
  17. llvm/
  18. llvm-libgcc/
  19. mlir/
  20. offload/
  21. openmp/
  22. polly/
  23. pstl/
  24. runtimes/
  25. third-party/
  26. utils/
  27. .clang-format
  28. .clang-tidy
  29. .git-blame-ignore-revs
  30. .gitattributes
  31. .gitignore
  32. .mailmap
  33. CODE_OF_CONDUCT.md
  34. CONTRIBUTING.md
  35. LICENSE.TXT
  36. pyproject.toml
  37. README.md
  38. SECURITY.md
README.md

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