)]}'
{
  "commit": "450737fba25203c8dfeca036925e9af9d6c22f0a",
  "tree": "06789ed2bc773275a2886d205e93b37b4c54e0e1",
  "parents": [
    "64dba812a3a8fc86b4ddbf34ad5bc5b5329cfca8"
  ],
  "author": {
    "name": "Austin Kerbow",
    "email": "Austin.Kerbow@amd.com",
    "time": "Tue Feb 25 19:37:46 2025 -0800"
  },
  "committer": {
    "name": "Austin Kerbow",
    "email": "Austin.Kerbow@amd.com",
    "time": "Mon Sep 15 22:51:53 2025 -0700"
  },
  "message": "[TargetInstrInfo] Add target hook for InstrSchedModel latency. [NFCI]\n\nThese hooks already exist when using instruction itineraries for latency\ninfo, this patch adds them for the newer TargetSchedModel.\n\nAllows targets to dynamically set latency values in the DAG builder.\nThis is useful in multi-pass schedulers like in the AMDGUP backend where\nwe may want to schedule a region multiple times with a different machine\nmodel or tweaked latencies for a specific instruction type.\n",
  "tree_diff": [
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      "new_path": "llvm/include/llvm/CodeGen/TargetInstrInfo.h"
    },
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      "new_path": "llvm/include/llvm/CodeGen/TargetSchedule.h"
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    },
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}