| commit | 6cf5acc3a55848f6f323d8798db8a32146c26a89 | [log] [tgz] |
|---|---|---|
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | Tue Dec 17 08:27:37 2024 +0700 |
| committer | Matt Arsenault <138339+arsenm@users.noreply.github.com> | Mon Jan 06 16:15:04 2025 +0000 |
| tree | 3fd25cc3c01d637d7db325b30c7042887cd1fe79 | |
| parent | 93220e7e06473a11bf48fee26bcea16cc527e5dc [diff] |
RegAllocGreedy: Fix subrange based instruction split logic Fix the logic for readsLaneSubset. Check at the correct point for the use operands of the instruction, instead of the result. Only consider the use register operands, and stop considering whether the subranges are actually live at this point. This avoids some unproductive splits. This also happens to avoid a use after free due to a split of an unspillable register. That issue still exists if the instruction does not reference the full set of register lanes.
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