; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck -check-prefix=GFX9 %s
; RUN: llc -mtriple=amdgpu12.00-amd-amdhsa -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
; RUN: llc -mtriple=amdgpu12.00-amd-amdhsa -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s

define i16 @test_bitextract_var(b32 %src, i32 %off) {
; GFX9-LABEL: test_bitextract_var:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_lshrrev_b32_e32 v0, v1, v0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitextract_var:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_lshrrev_b32_e32 v0, v1, v0
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitextract i16, b32 %src, i32 %off
  ret i16 %result
}

define i16 @test_bitextract_const(b32 %src) {
; GFX9-LABEL: test_bitextract_const:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitextract_const:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitextract i16, b32 %src, i32 8
  ret i16 %result
}

define i8 @test_bitextract_narrow(b64 %src) {
; GFX9-LABEL: test_bitextract_narrow:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitextract_narrow:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitextract i8, b64 %src, i32 0
  ret i8 %result
}

define i1 @test_bitextract_b1(b1 %src) {
; GFX9-LABEL: test_bitextract_b1:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitextract_b1:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitextract i1, b1 %src, i32 0
  ret i1 %result
}

define i8 @test_bitextract_b37(b37 %src, i32 %off) {
; GFX9-LABEL: test_bitextract_b37:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_and_b32_e32 v1, 31, v1
; GFX9-NEXT:    v_lshrrev_b64 v[0:1], v2, v[0:1]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitextract_b37:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_and_b32_e32 v1, 31, v1
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT:    v_lshrrev_b64 v[0:1], v2, v[0:1]
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitextract i8, b37 %src, i32 %off
  ret i8 %result
}

define i8 @test_bitextract_b37_const(b37 %src) {
; GFX9-LABEL: test_bitextract_b37_const:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_lshrrev_b64 v[0:1], 20, v[0:1]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitextract_b37_const:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_lshrrev_b64 v[0:1], 20, v[0:1]
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitextract i8, b37 %src, i32 20
  ret i8 %result
}

define i16 @test_bitextract_b87(b87 %src, i32 %off) {
; GFX9-LABEL: test_bitextract_b87:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_and_b32_e32 v4, 0x7fffff, v2
; GFX9-NEXT:    v_mov_b32_e32 v5, 0
; GFX9-NEXT:    v_sub_u32_e32 v2, 64, v3
; GFX9-NEXT:    v_subrev_u32_e32 v8, 64, v3
; GFX9-NEXT:    v_lshlrev_b64 v[6:7], v2, v[4:5]
; GFX9-NEXT:    v_lshrrev_b64 v[1:2], v3, v[0:1]
; GFX9-NEXT:    v_lshrrev_b64 v[4:5], v8, v[4:5]
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v6
; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitextract_b87:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v4, 0x7fffff, v2
; GFX12-NEXT:    v_sub_nc_u32_e32 v2, 64, v3
; GFX12-NEXT:    v_subrev_nc_u32_e32 v8, 64, v3
; GFX12-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 64, v3
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX12-NEXT:    v_lshlrev_b64_e32 v[6:7], v2, v[4:5]
; GFX12-NEXT:    v_lshrrev_b64 v[1:2], v3, v[0:1]
; GFX12-NEXT:    v_lshrrev_b64 v[4:5], v8, v[4:5]
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-NEXT:    v_or_b32_e32 v1, v1, v6
; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc_lo
; GFX12-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v3
; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitextract i16, b87 %src, i32 %off
  ret i16 %result
}


define i32 @test_bitextract_b128(b128 %src, i32 %off) {
; GFX9-LABEL: test_bitextract_b128:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_sub_u32_e32 v5, 64, v4
; GFX9-NEXT:    v_lshlrev_b64 v[5:6], v5, v[2:3]
; GFX9-NEXT:    v_lshrrev_b64 v[6:7], v4, v[0:1]
; GFX9-NEXT:    v_subrev_u32_e32 v1, 64, v4
; GFX9-NEXT:    v_lshrrev_b64 v[1:2], v1, v[2:3]
; GFX9-NEXT:    v_or_b32_e32 v5, v6, v5
; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitextract_b128:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_sub_nc_u32_e32 v7, 64, v4
; GFX12-NEXT:    v_lshrrev_b64 v[5:6], v4, v[0:1]
; GFX12-NEXT:    v_subrev_nc_u32_e32 v1, 64, v4
; GFX12-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 64, v4
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-NEXT:    v_lshlrev_b64_e32 v[6:7], v7, v[2:3]
; GFX12-NEXT:    v_lshrrev_b64 v[1:2], v1, v[2:3]
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-NEXT:    v_or_b32_e32 v2, v5, v6
; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX12-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v4
; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitextract i32, b128 %src, i32 %off
  ret i32 %result
}

define i32 @test_bitextract_b231(b231 %src, i32 %off) {
; GFX9-LABEL: test_bitextract_b231:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v9, 0
; GFX9-NEXT:    v_and_b32_e32 v7, 0x7f, v7
; GFX9-NEXT:    buffer_store_dword v9, off, s[0:3], s32 offset:56
; GFX9-NEXT:    buffer_store_dword v9, off, s[0:3], s32 offset:48
; GFX9-NEXT:    buffer_store_dword v9, off, s[0:3], s32 offset:40
; GFX9-NEXT:    buffer_store_dword v9, off, s[0:3], s32 offset:32
; GFX9-NEXT:    buffer_store_dword v6, off, s[0:3], s32 offset:24
; GFX9-NEXT:    buffer_store_dword v4, off, s[0:3], s32 offset:16
; GFX9-NEXT:    buffer_store_dword v2, off, s[0:3], s32 offset:8
; GFX9-NEXT:    buffer_store_dword v0, off, s[0:3], s32
; GFX9-NEXT:    buffer_store_dword v9, off, s[0:3], s32 offset:60
; GFX9-NEXT:    buffer_store_dword v9, off, s[0:3], s32 offset:52
; GFX9-NEXT:    buffer_store_dword v9, off, s[0:3], s32 offset:44
; GFX9-NEXT:    buffer_store_dword v9, off, s[0:3], s32 offset:36
; GFX9-NEXT:    buffer_store_dword v5, off, s[0:3], s32 offset:20
; GFX9-NEXT:    buffer_store_dword v3, off, s[0:3], s32 offset:12
; GFX9-NEXT:    buffer_store_dword v1, off, s[0:3], s32 offset:4
; GFX9-NEXT:    buffer_store_dword v7, off, s[0:3], s32 offset:28
; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 3, v8
; GFX9-NEXT:    v_and_b32_e32 v0, 24, v0
; GFX9-NEXT:    v_lshrrev_b32_e64 v1, 6, s32
; GFX9-NEXT:    v_add_u32_e32 v2, v0, v1
; GFX9-NEXT:    buffer_load_dword v3, v2, s[0:3], 0 offen offset:8
; GFX9-NEXT:    buffer_load_dword v0, v2, s[0:3], 0 offen
; GFX9-NEXT:    buffer_load_dword v1, v2, s[0:3], 0 offen offset:4
; GFX9-NEXT:    v_and_b32_e32 v2, 63, v8
; GFX9-NEXT:    v_xor_b32_e32 v4, 63, v2
; GFX9-NEXT:    s_waitcnt vmcnt(2)
; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 1, v3
; GFX9-NEXT:    v_lshlrev_b64 v[2:3], v4, v[2:3]
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    v_lshrrev_b64 v[0:1], v8, v[0:1]
; GFX9-NEXT:    v_or_b32_e32 v0, v0, v2
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitextract_b231:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    s_mov_b32 s0, 0
; GFX12-NEXT:    v_lshrrev_b32_e32 v11, 3, v8
; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT:    s_mov_b32 s1, s0
; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT:    v_dual_mov_b32 v10, s1 :: v_dual_and_b32 v7, 0x7f, v7
; GFX12-NEXT:    v_mov_b32_e32 v9, s0
; GFX12-NEXT:    s_clause 0x3
; GFX12-NEXT:    scratch_store_b64 off, v[4:5], s32 offset:16
; GFX12-NEXT:    scratch_store_b64 off, v[2:3], s32 offset:8
; GFX12-NEXT:    scratch_store_b64 off, v[0:1], s32
; GFX12-NEXT:    scratch_store_b64 off, v[6:7], s32 offset:24
; GFX12-NEXT:    v_and_b32_e32 v3, 63, v8
; GFX12-NEXT:    s_clause 0x3
; GFX12-NEXT:    scratch_store_b64 off, v[9:10], s32 offset:56
; GFX12-NEXT:    scratch_store_b64 off, v[9:10], s32 offset:48
; GFX12-NEXT:    scratch_store_b64 off, v[9:10], s32 offset:40
; GFX12-NEXT:    scratch_store_b64 off, v[9:10], s32 offset:32
; GFX12-NEXT:    v_and_b32_e32 v9, 24, v11
; GFX12-NEXT:    v_xor_b32_e32 v3, 63, v3
; GFX12-NEXT:    s_clause 0x1
; GFX12-NEXT:    scratch_load_b32 v2, v9, s32 offset:8
; GFX12-NEXT:    scratch_load_b64 v[0:1], v9, s32
; GFX12-NEXT:    s_wait_loadcnt 0x1
; GFX12-NEXT:    v_lshlrev_b32_e32 v2, 1, v2
; GFX12-NEXT:    s_wait_loadcnt 0x0
; GFX12-NEXT:    v_lshrrev_b64 v[0:1], v8, v[0:1]
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT:    v_lshlrev_b64_e32 v[2:3], v3, v[2:3]
; GFX12-NEXT:    v_or_b32_e32 v0, v0, v2
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitextract i32, b231 %src, i32 %off
  ret i32 %result
}


; Bitinsert
define b32 @test_bitinsert_var(b32 %base, i16 %val, i32 %off) {
; GFX9-LABEL: test_bitinsert_var:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_mov_b32 s4, 0xffff
; GFX9-NEXT:    v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT:    v_lshlrev_b32_e64 v2, v2, s4
; GFX9-NEXT:    v_not_b32_e32 v2, v2
; GFX9-NEXT:    v_and_or_b32 v0, v0, v2, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_bitinsert_var:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cvt_u32_u16_e32 v1, v1.l
; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e64 v3, v2, 0xffff
; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, v2, v1
; GFX12-TRUE16-NEXT:    v_not_b32_e32 v2, v3
; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT:    v_and_or_b32 v0, v0, v2, v1
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_bitinsert_var:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e64 v3, v2, 0xffff
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, v2, v1
; GFX12-FAKE16-NEXT:    v_not_b32_e32 v2, v3
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT:    v_and_or_b32 v0, v0, v2, v1
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b32 %base, i16 %val, i32 %off
  ret b32 %result
}

define b1 @test_bitinsert_b1(b1 %base, i1 %val) {
; GFX9-LABEL: test_bitinsert_b1:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v0, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_b1:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_mov_b32_e32 v0, v1
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b1 %base, i1 %val, i32 0
  ret b1 %result
}

define b37 @test_bitinsert_b37_var(b37 %base, i8 %val, i32 %off) {
; GFX9-LABEL: test_bitinsert_b37_var:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_mov_b64 s[4:5], 0xff
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], v3, s[4:5]
; GFX9-NEXT:    v_xor_b32_e32 v5, 31, v5
; GFX9-NEXT:    v_and_b32_e32 v5, v1, v5
; GFX9-NEXT:    v_and_b32_e32 v1, 0xff, v2
; GFX9-NEXT:    v_mov_b32_e32 v2, 0
; GFX9-NEXT:    v_not_b32_e32 v4, v4
; GFX9-NEXT:    v_lshlrev_b64 v[2:3], v3, v[1:2]
; GFX9-NEXT:    v_and_b32_e32 v0, v0, v4
; GFX9-NEXT:    v_or_b32_e32 v1, v5, v3
; GFX9-NEXT:    v_or_b32_e32 v0, v0, v2
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_b37_var:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_lshlrev_b64_e64 v[4:5], v3, 0xff
; GFX12-NEXT:    v_dual_mov_b32 v7, 0 :: v_dual_and_b32 v6, 0xff, v2
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-NEXT:    v_not_b32_e32 v4, v4
; GFX12-NEXT:    v_xor_b32_e32 v5, 31, v5
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-NEXT:    v_lshlrev_b64_e32 v[2:3], v3, v[6:7]
; GFX12-NEXT:    v_and_b32_e32 v0, v0, v4
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT:    v_and_b32_e32 v1, v1, v5
; GFX12-NEXT:    v_or_b32_e32 v0, v0, v2
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b37 %base, i8 %val, i32 %off
  ret b37 %result
}

define b87 @test_bitinsert_b87_var(b87 %base, i16 %val, i32 %off) {
; GFX9-LABEL: test_bitinsert_b87_var:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_mov_b64 s[4:5], 0xffff
; GFX9-NEXT:    v_lshlrev_b64 v[5:6], v4, s[4:5]
; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v4
; GFX9-NEXT:    s_mov_b32 s6, 0
; GFX9-NEXT:    v_cndmask_b32_e32 v6, 0, v6, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v9, 0, v5, vcc
; GFX9-NEXT:    v_bfi_b32 v1, v6, 0, v1
; GFX9-NEXT:    v_and_b32_e32 v5, 0xffff, v3
; GFX9-NEXT:    v_mov_b32_e32 v6, s6
; GFX9-NEXT:    v_lshlrev_b64 v[7:8], v4, v[5:6]
; GFX9-NEXT:    v_bfi_b32 v0, v9, 0, v0
; GFX9-NEXT:    v_cndmask_b32_e32 v3, 0, v8, vcc
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX9-NEXT:    v_sub_u32_e32 v3, 64, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v9, 0, v7, vcc
; GFX9-NEXT:    v_lshrrev_b64 v[7:8], v3, v[5:6]
; GFX9-NEXT:    v_subrev_u32_e32 v8, 64, v4
; GFX9-NEXT:    v_lshlrev_b64 v[5:6], v8, v[5:6]
; GFX9-NEXT:    v_or_b32_e32 v0, v0, v9
; GFX9-NEXT:    v_cndmask_b32_e32 v9, v5, v7, vcc
; GFX9-NEXT:    v_lshrrev_b64 v[5:6], v3, s[4:5]
; GFX9-NEXT:    v_lshlrev_b64 v[6:7], v8, s[4:5]
; GFX9-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v6, v5, vcc
; GFX9-NEXT:    v_cndmask_b32_e64 v4, v4, 0, s[4:5]
; GFX9-NEXT:    v_cndmask_b32_e64 v3, v9, 0, s[4:5]
; GFX9-NEXT:    v_not_b32_e32 v4, v4
; GFX9-NEXT:    v_and_or_b32 v2, v2, v4, v3
; GFX9-NEXT:    v_and_b32_e32 v2, 0x7fffff, v2
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_bitinsert_b87_var:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_sub_nc_u32_e32 v12, 64, v4
; GFX12-TRUE16-NEXT:    v_subrev_nc_u32_e32 v13, 64, v4
; GFX12-TRUE16-NEXT:    s_mov_b32 s0, 0
; GFX12-TRUE16-NEXT:    v_cvt_u32_u16_e32 v5, v3.l
; GFX12-TRUE16-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 64, v4
; GFX12-TRUE16-NEXT:    v_lshrrev_b64 v[9:10], v12, 0xffff
; GFX12-TRUE16-NEXT:    v_lshlrev_b64_e64 v[10:11], v13, 0xffff
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v6, s0
; GFX12-TRUE16-NEXT:    v_lshlrev_b64_e64 v[7:8], v4, 0xffff
; GFX12-TRUE16-NEXT:    v_cmp_eq_u32_e64 s0, 0, v4
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v10, v9, vcc_lo
; GFX12-TRUE16-NEXT:    v_lshrrev_b64 v[11:12], v12, v[5:6]
; GFX12-TRUE16-NEXT:    v_lshlrev_b64_e32 v[12:13], v13, v[5:6]
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e32 v8, 0, v8, vcc_lo
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v10, v3, 0, s0
; GFX12-TRUE16-NEXT:    v_lshlrev_b64_e32 v[3:4], v4, v[5:6]
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e32 v7, 0, v7, vcc_lo
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e32 v9, v12, v11, vcc_lo
; GFX12-TRUE16-NEXT:    v_bfi_b32 v1, v8, 0, v1
; GFX12-TRUE16-NEXT:    v_not_b32_e32 v5, v10
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc_lo
; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v9, v9, 0, s0
; GFX12-TRUE16-NEXT:    v_bfi_b32 v0, v7, 0, v0
; GFX12-TRUE16-NEXT:    v_or_b32_e32 v1, v1, v4
; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT:    v_and_or_b32 v2, v2, v5, v9
; GFX12-TRUE16-NEXT:    v_dual_cndmask_b32 v3, 0, v3 :: v_dual_and_b32 v2, 0x7fffff, v2
; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT:    v_or_b32_e32 v0, v0, v3
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_bitinsert_b87_var:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v6, s0 :: v_dual_and_b32 v5, 0xffff, v3
; GFX12-FAKE16-NEXT:    v_sub_nc_u32_e32 v3, 64, v4
; GFX12-FAKE16-NEXT:    v_subrev_nc_u32_e32 v13, 64, v4
; GFX12-FAKE16-NEXT:    v_lshlrev_b64_e64 v[7:8], v4, 0xffff
; GFX12-FAKE16-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 64, v4
; GFX12-FAKE16-NEXT:    v_cmp_eq_u32_e64 s0, 0, v4
; GFX12-FAKE16-NEXT:    v_lshrrev_b64 v[9:10], v3, v[5:6]
; GFX12-FAKE16-NEXT:    v_lshlrev_b64_e32 v[10:11], v13, v[5:6]
; GFX12-FAKE16-NEXT:    v_lshrrev_b64 v[11:12], v3, 0xffff
; GFX12-FAKE16-NEXT:    v_lshlrev_b64_e64 v[12:13], v13, 0xffff
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v8, 0, v8 :: v_dual_cndmask_b32 v3, v10, v9
; GFX12-FAKE16-NEXT:    v_bfi_b32 v1, v8, 0, v1
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_sdst(0)
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v10, v3, 0, s0
; GFX12-FAKE16-NEXT:    v_lshlrev_b64_e32 v[3:4], v4, v[5:6]
; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v9, v12, v11 :: v_dual_cndmask_b32 v4, 0, v4
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v9, v9, 0, s0
; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v3, 0, v3, vcc_lo
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-FAKE16-NEXT:    v_or_b32_e32 v1, v1, v4
; GFX12-FAKE16-NEXT:    v_not_b32_e32 v5, v9
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT:    v_and_or_b32 v2, v2, v5, v10
; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v7, 0, v7 :: v_dual_and_b32 v2, 0x7fffff, v2
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT:    v_bfi_b32 v0, v7, 0, v0
; GFX12-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v3
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b87 %base, i16 %val, i32 %off
  ret b87 %result
}

define b128 @test_bitinsert_b128_var(b128 %base, i32 %val, i32 %off) {
; GFX9-LABEL: test_bitinsert_b128_var:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v6, v5
; GFX9-NEXT:    v_sub_u32_e32 v11, 64, v6
; GFX9-NEXT:    s_mov_b64 s[6:7], 0xffffffff
; GFX9-NEXT:    v_subrev_u32_e32 v12, 64, v6
; GFX9-NEXT:    v_lshrrev_b64 v[7:8], v11, s[6:7]
; GFX9-NEXT:    v_lshlrev_b64 v[9:10], v12, s[6:7]
; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v6
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v10, v8, vcc
; GFX9-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v6
; GFX9-NEXT:    v_cndmask_b32_e64 v5, v5, 0, s[4:5]
; GFX9-NEXT:    v_cndmask_b32_e32 v7, v9, v7, vcc
; GFX9-NEXT:    v_bfi_b32 v3, v5, 0, v3
; GFX9-NEXT:    v_mov_b32_e32 v5, 0
; GFX9-NEXT:    v_cndmask_b32_e64 v13, v7, 0, s[4:5]
; GFX9-NEXT:    v_lshrrev_b64 v[7:8], v11, v[4:5]
; GFX9-NEXT:    v_lshlrev_b64 v[9:10], v12, v[4:5]
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], v6, v[4:5]
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc
; GFX9-NEXT:    v_cndmask_b32_e64 v8, v8, 0, s[4:5]
; GFX9-NEXT:    v_cndmask_b32_e32 v7, v9, v7, vcc
; GFX9-NEXT:    v_cndmask_b32_e64 v9, v7, 0, s[4:5]
; GFX9-NEXT:    v_or_b32_e32 v3, v3, v8
; GFX9-NEXT:    v_lshlrev_b64 v[7:8], v6, s[6:7]
; GFX9-NEXT:    v_bfi_b32 v2, v13, 0, v2
; GFX9-NEXT:    v_cndmask_b32_e32 v8, 0, v8, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v7, 0, v7, vcc
; GFX9-NEXT:    v_bfi_b32 v1, v8, 0, v1
; GFX9-NEXT:    v_bfi_b32 v0, v7, 0, v0
; GFX9-NEXT:    v_cndmask_b32_e32 v5, 0, v5, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
; GFX9-NEXT:    v_or_b32_e32 v2, v2, v9
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v5
; GFX9-NEXT:    v_or_b32_e32 v0, v0, v4
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_b128_var:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dual_mov_b32 v6, v5 :: v_dual_mov_b32 v5, 0
; GFX12-NEXT:    s_mov_b64 s[2:3], 0xffffffff
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT:    v_sub_nc_u32_e32 v11, 64, v6
; GFX12-NEXT:    v_subrev_nc_u32_e32 v12, 64, v6
; GFX12-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 64, v6
; GFX12-NEXT:    v_cmp_eq_u32_e64 s0, 0, v6
; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT:    v_lshrrev_b64 v[7:8], v11, s[2:3]
; GFX12-NEXT:    v_lshlrev_b64_e64 v[9:10], v12, s[2:3]
; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT:    v_dual_cndmask_b32 v13, v10, v8 :: v_dual_cndmask_b32 v14, v9, v7
; GFX12-NEXT:    v_lshlrev_b64_e64 v[7:8], v6, s[2:3]
; GFX12-NEXT:    v_lshrrev_b64 v[9:10], v11, v[4:5]
; GFX12-NEXT:    v_lshlrev_b64_e32 v[11:12], v12, v[4:5]
; GFX12-NEXT:    v_lshlrev_b64_e32 v[4:5], v6, v[4:5]
; GFX12-NEXT:    s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT:    v_cndmask_b32_e64 v13, v13, 0, s0
; GFX12-NEXT:    v_cndmask_b32_e64 v14, v14, 0, s0
; GFX12-NEXT:    v_dual_cndmask_b32 v6, 0, v8 :: v_dual_cndmask_b32 v7, 0, v7
; GFX12-NEXT:    v_dual_cndmask_b32 v8, v12, v10 :: v_dual_cndmask_b32 v9, v11, v9
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-NEXT:    v_bfi_b32 v3, v13, 0, v3
; GFX12-NEXT:    v_bfi_b32 v2, v14, 0, v2
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX12-NEXT:    v_bfi_b32 v1, v6, 0, v1
; GFX12-NEXT:    v_bfi_b32 v0, v7, 0, v0
; GFX12-NEXT:    v_dual_cndmask_b32 v4, 0, v4 :: v_dual_cndmask_b32 v5, 0, v5
; GFX12-NEXT:    v_cndmask_b32_e64 v6, v9, 0, s0
; GFX12-NEXT:    v_cndmask_b32_e64 v7, v8, 0, s0
; GFX12-NEXT:    v_or_b32_e32 v0, v0, v4
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-NEXT:    v_or_b32_e32 v1, v1, v5
; GFX12-NEXT:    v_or_b32_e32 v2, v2, v6
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4)
; GFX12-NEXT:    v_or_b32_e32 v3, v3, v7
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b128 %base, i32 %val, i32 %off
  ret b128 %result
}

define b231 @test_bitinsert_b231_var(b231 %base, i32 %val, i32 %off) {
; GFX9-LABEL: test_bitinsert_b231_var:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v10, 0
; GFX9-NEXT:    v_mov_b32_e32 v11, -1
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:60
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:52
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:44
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:36
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:28
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:20
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:12
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:4
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:56
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:48
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:40
; GFX9-NEXT:    buffer_store_dword v11, off, s[0:3], s32 offset:32
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:24
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:16
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:8
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:124
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:116
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:108
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:92
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:84
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:76
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:68
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:100
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:120
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:112
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:104
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:88
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:80
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:72
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:64
; GFX9-NEXT:    buffer_store_dword v8, off, s[0:3], s32 offset:96
; GFX9-NEXT:    s_lshr_b32 s5, s32, 6
; GFX9-NEXT:    v_lshrrev_b32_e32 v8, 3, v9
; GFX9-NEXT:    s_add_i32 s4, s5, 32
; GFX9-NEXT:    v_and_b32_e32 v8, 24, v8
; GFX9-NEXT:    v_sub_u32_e32 v18, s4, v8
; GFX9-NEXT:    buffer_load_dword v11, v18, s[0:3], 0 offen offset:28
; GFX9-NEXT:    buffer_load_dword v13, v18, s[0:3], 0 offen offset:20
; GFX9-NEXT:    buffer_load_dword v12, v18, s[0:3], 0 offen offset:16
; GFX9-NEXT:    buffer_load_dword v10, v18, s[0:3], 0 offen offset:24
; GFX9-NEXT:    v_and_b32_e32 v14, 63, v9
; GFX9-NEXT:    s_lshr_b32 s5, s32, 6
; GFX9-NEXT:    v_xor_b32_e32 v24, 63, v14
; GFX9-NEXT:    s_add_i32 s4, s5, 0x60
; GFX9-NEXT:    v_sub_u32_e32 v8, s4, v8
; GFX9-NEXT:    buffer_load_dword v15, v18, s[0:3], 0 offen offset:12
; GFX9-NEXT:    s_waitcnt vmcnt(2)
; GFX9-NEXT:    v_lshrrev_b64 v[16:17], 1, v[12:13]
; GFX9-NEXT:    s_waitcnt vmcnt(1)
; GFX9-NEXT:    v_lshlrev_b64 v[10:11], v9, v[10:11]
; GFX9-NEXT:    v_lshrrev_b64 v[16:17], v24, v[16:17]
; GFX9-NEXT:    v_lshlrev_b64 v[12:13], v9, v[12:13]
; GFX9-NEXT:    v_or_b32_e32 v14, v11, v17
; GFX9-NEXT:    v_or_b32_e32 v20, v10, v16
; GFX9-NEXT:    buffer_load_dword v11, v8, s[0:3], 0 offen offset:28
; GFX9-NEXT:    buffer_load_dword v17, v8, s[0:3], 0 offen offset:20
; GFX9-NEXT:    buffer_load_dword v16, v8, s[0:3], 0 offen offset:16
; GFX9-NEXT:    buffer_load_dword v10, v8, s[0:3], 0 offen offset:24
; GFX9-NEXT:    buffer_load_dword v19, v8, s[0:3], 0 offen offset:12
; GFX9-NEXT:    v_xor_b32_e32 v14, 0x7f, v14
; GFX9-NEXT:    v_not_b32_e32 v20, v20
; GFX9-NEXT:    v_and_b32_e32 v14, v7, v14
; GFX9-NEXT:    v_and_b32_e32 v20, v6, v20
; GFX9-NEXT:    s_waitcnt vmcnt(2)
; GFX9-NEXT:    v_lshrrev_b64 v[6:7], 1, v[16:17]
; GFX9-NEXT:    s_waitcnt vmcnt(1)
; GFX9-NEXT:    v_lshlrev_b64 v[10:11], v9, v[10:11]
; GFX9-NEXT:    v_lshrrev_b64 v[6:7], v24, v[6:7]
; GFX9-NEXT:    v_or3_b32 v7, v11, v7, v14
; GFX9-NEXT:    v_or3_b32 v6, v10, v6, v20
; GFX9-NEXT:    buffer_load_dword v11, v18, s[0:3], 0 offen offset:4
; GFX9-NEXT:    buffer_load_dword v14, v18, s[0:3], 0 offen offset:8
; GFX9-NEXT:    buffer_load_dword v10, v18, s[0:3], 0 offen
; GFX9-NEXT:    s_waitcnt vmcnt(1)
; GFX9-NEXT:    v_lshlrev_b64 v[22:23], v9, v[14:15]
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    v_lshrrev_b64 v[20:21], 1, v[10:11]
; GFX9-NEXT:    v_lshrrev_b64 v[14:15], 1, v[14:15]
; GFX9-NEXT:    v_lshrrev_b64 v[20:21], v24, v[20:21]
; GFX9-NEXT:    v_lshrrev_b64 v[14:15], v24, v[14:15]
; GFX9-NEXT:    v_or_b32_e32 v23, v23, v21
; GFX9-NEXT:    v_or_b32_e32 v22, v22, v20
; GFX9-NEXT:    buffer_load_dword v18, v8, s[0:3], 0 offen offset:8
; GFX9-NEXT:    buffer_load_dword v21, v8, s[0:3], 0 offen offset:4
; GFX9-NEXT:    buffer_load_dword v20, v8, s[0:3], 0 offen
; GFX9-NEXT:    v_bfi_b32 v8, v23, 0, v3
; GFX9-NEXT:    v_bfi_b32 v25, v22, 0, v2
; GFX9-NEXT:    v_lshlrev_b64 v[10:11], v9, v[10:11]
; GFX9-NEXT:    v_bfi_b32 v1, v11, 0, v1
; GFX9-NEXT:    v_bfi_b32 v0, v10, 0, v0
; GFX9-NEXT:    s_waitcnt vmcnt(2)
; GFX9-NEXT:    v_lshlrev_b64 v[22:23], v9, v[18:19]
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    v_lshrrev_b64 v[2:3], 1, v[20:21]
; GFX9-NEXT:    v_lshrrev_b64 v[2:3], v24, v[2:3]
; GFX9-NEXT:    v_or3_b32 v3, v23, v3, v8
; GFX9-NEXT:    v_or3_b32 v2, v22, v2, v25
; GFX9-NEXT:    v_or_b32_e32 v8, v13, v15
; GFX9-NEXT:    v_or_b32_e32 v22, v12, v14
; GFX9-NEXT:    v_lshrrev_b64 v[12:13], 1, v[18:19]
; GFX9-NEXT:    v_bfi_b32 v5, v8, 0, v5
; GFX9-NEXT:    v_lshrrev_b64 v[12:13], v24, v[12:13]
; GFX9-NEXT:    v_lshlrev_b64 v[14:15], v9, v[16:17]
; GFX9-NEXT:    v_lshlrev_b64 v[8:9], v9, v[20:21]
; GFX9-NEXT:    v_bfi_b32 v4, v22, 0, v4
; GFX9-NEXT:    v_or3_b32 v5, v15, v13, v5
; GFX9-NEXT:    v_or3_b32 v4, v14, v12, v4
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v9
; GFX9-NEXT:    v_or_b32_e32 v0, v0, v8
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_b231_var:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    s_mov_b32 s0, 0
; GFX12-NEXT:    v_mov_b32_e32 v14, 0
; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT:    s_mov_b32 s1, s0
; GFX12-NEXT:    v_dual_mov_b32 v10, v9 :: v_dual_mov_b32 v11, s0
; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT:    v_dual_mov_b32 v12, s1 :: v_dual_mov_b32 v13, -1
; GFX12-NEXT:    s_add_co_i32 s0, s32, 32
; GFX12-NEXT:    s_add_co_i32 s1, s32, 0x60
; GFX12-NEXT:    s_clause 0x3
; GFX12-NEXT:    scratch_store_b64 off, v[11:12], s32 offset:56
; GFX12-NEXT:    scratch_store_b64 off, v[11:12], s32 offset:48
; GFX12-NEXT:    scratch_store_b64 off, v[11:12], s32 offset:40
; GFX12-NEXT:    scratch_store_b64 off, v[13:14], s32 offset:32
; GFX12-NEXT:    v_lshrrev_b32_e32 v13, 3, v10
; GFX12-NEXT:    s_clause 0x7
; GFX12-NEXT:    scratch_store_b64 off, v[11:12], s32 offset:24
; GFX12-NEXT:    scratch_store_b64 off, v[11:12], s32 offset:16
; GFX12-NEXT:    scratch_store_b64 off, v[11:12], s32 offset:8
; GFX12-NEXT:    scratch_store_b64 off, v[11:12], s32
; GFX12-NEXT:    scratch_store_b64 off, v[11:12], s32 offset:88
; GFX12-NEXT:    scratch_store_b64 off, v[11:12], s32 offset:80
; GFX12-NEXT:    scratch_store_b64 off, v[11:12], s32 offset:72
; GFX12-NEXT:    scratch_store_b64 off, v[11:12], s32 offset:64
; GFX12-NEXT:    v_and_b32_e32 v25, 63, v10
; GFX12-NEXT:    v_and_b32_e32 v13, 24, v13
; GFX12-NEXT:    v_mov_b32_e32 v9, v14
; GFX12-NEXT:    s_clause 0x3
; GFX12-NEXT:    scratch_store_b64 off, v[11:12], s32 offset:120
; GFX12-NEXT:    scratch_store_b64 off, v[11:12], s32 offset:112
; GFX12-NEXT:    scratch_store_b64 off, v[11:12], s32 offset:104
; GFX12-NEXT:    scratch_store_b64 off, v[8:9], s32 offset:96
; GFX12-NEXT:    v_xor_b32_e32 v37, 63, v25
; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT:    v_sub_nc_u32_e32 v19, s0, v13
; GFX12-NEXT:    v_sub_nc_u32_e32 v23, s1, v13
; GFX12-NEXT:    s_clause 0x1
; GFX12-NEXT:    scratch_load_b64 v[8:9], v19, off offset:24
; GFX12-NEXT:    scratch_load_b64 v[11:12], v19, off offset:16
; GFX12-NEXT:    s_clause 0x1
; GFX12-NEXT:    scratch_load_b64 v[13:14], v23, off offset:24
; GFX12-NEXT:    scratch_load_b64 v[15:16], v23, off offset:16
; GFX12-NEXT:    s_clause 0x1
; GFX12-NEXT:    scratch_load_b64 v[17:18], v19, off offset:8
; GFX12-NEXT:    scratch_load_b64 v[19:20], v19, off
; GFX12-NEXT:    s_clause 0x1
; GFX12-NEXT:    scratch_load_b64 v[21:22], v23, off offset:8
; GFX12-NEXT:    scratch_load_b64 v[23:24], v23, off
; GFX12-NEXT:    s_wait_loadcnt 0x7
; GFX12-NEXT:    v_lshlrev_b64_e32 v[8:9], v10, v[8:9]
; GFX12-NEXT:    s_wait_loadcnt 0x6
; GFX12-NEXT:    v_lshrrev_b64 v[25:26], 1, v[11:12]
; GFX12-NEXT:    v_lshlrev_b64_e32 v[11:12], v10, v[11:12]
; GFX12-NEXT:    s_wait_loadcnt 0x4
; GFX12-NEXT:    v_lshrrev_b64 v[27:28], 1, v[15:16]
; GFX12-NEXT:    s_wait_loadcnt 0x3
; GFX12-NEXT:    v_lshlrev_b64_e32 v[29:30], v10, v[17:18]
; GFX12-NEXT:    s_wait_loadcnt 0x2
; GFX12-NEXT:    v_lshrrev_b64 v[31:32], 1, v[19:20]
; GFX12-NEXT:    v_lshrrev_b64 v[17:18], 1, v[17:18]
; GFX12-NEXT:    v_lshlrev_b64_e32 v[19:20], v10, v[19:20]
; GFX12-NEXT:    v_lshrrev_b64 v[25:26], v37, v[25:26]
; GFX12-NEXT:    s_wait_loadcnt 0x0
; GFX12-NEXT:    v_lshrrev_b64 v[35:36], 1, v[23:24]
; GFX12-NEXT:    v_lshlrev_b64_e32 v[23:24], v10, v[23:24]
; GFX12-NEXT:    v_lshrrev_b64 v[31:32], v37, v[31:32]
; GFX12-NEXT:    v_lshrrev_b64 v[17:18], v37, v[17:18]
; GFX12-NEXT:    v_bfi_b32 v0, v19, 0, v0
; GFX12-NEXT:    v_or_b32_e32 v9, v9, v26
; GFX12-NEXT:    v_or_b32_e32 v8, v8, v25
; GFX12-NEXT:    v_lshlrev_b64_e32 v[33:34], v10, v[21:22]
; GFX12-NEXT:    v_lshrrev_b64 v[21:22], 1, v[21:22]
; GFX12-NEXT:    v_lshlrev_b64_e32 v[13:14], v10, v[13:14]
; GFX12-NEXT:    v_lshlrev_b64_e32 v[15:16], v10, v[15:16]
; GFX12-NEXT:    v_or_b32_e32 v0, v0, v23
; GFX12-NEXT:    v_or_b32_e32 v10, v30, v32
; GFX12-NEXT:    v_or_b32_e32 v23, v29, v31
; GFX12-NEXT:    v_or_b32_e32 v12, v12, v18
; GFX12-NEXT:    v_or_b32_e32 v11, v11, v17
; GFX12-NEXT:    v_xor_b32_e32 v9, 0x7f, v9
; GFX12-NEXT:    v_not_b32_e32 v8, v8
; GFX12-NEXT:    v_lshrrev_b64 v[27:28], v37, v[27:28]
; GFX12-NEXT:    v_bfi_b32 v1, v20, 0, v1
; GFX12-NEXT:    v_lshrrev_b64 v[19:20], v37, v[35:36]
; GFX12-NEXT:    v_lshrrev_b64 v[21:22], v37, v[21:22]
; GFX12-NEXT:    v_bfi_b32 v3, v10, 0, v3
; GFX12-NEXT:    v_bfi_b32 v2, v23, 0, v2
; GFX12-NEXT:    v_bfi_b32 v5, v12, 0, v5
; GFX12-NEXT:    v_bfi_b32 v4, v11, 0, v4
; GFX12-NEXT:    v_and_b32_e32 v7, v7, v9
; GFX12-NEXT:    v_and_b32_e32 v6, v6, v8
; GFX12-NEXT:    v_or_b32_e32 v1, v1, v24
; GFX12-NEXT:    v_or3_b32 v3, v34, v20, v3
; GFX12-NEXT:    v_or3_b32 v2, v33, v19, v2
; GFX12-NEXT:    v_or3_b32 v5, v16, v22, v5
; GFX12-NEXT:    v_or3_b32 v4, v15, v21, v4
; GFX12-NEXT:    v_or3_b32 v7, v14, v28, v7
; GFX12-NEXT:    v_or3_b32 v6, v13, v27, v6
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b231 %base, i32 %val, i32 %off
  ret b231 %result
}


; different inserted value widths

define b1 @test_bitinsert_b1_var(b1 %base, i1 %val, i32 %off) {
; GFX9-LABEL: test_bitinsert_b1_var:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v0, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_b1_var:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_mov_b32_e32 v0, v1
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b1 %base, i1 %val, i32 %off
  ret b1 %result
}

define b8 @test_bitinsert_b8_var(b8 %base, i4 %val, i32 %off) {
; GFX9-LABEL: test_bitinsert_b8_var:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_and_b32_e32 v1, 15, v1
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, v2, v1
; GFX9-NEXT:    v_lshlrev_b16_e64 v2, v2, 15
; GFX9-NEXT:    v_xor_b32_e32 v2, -1, v2
; GFX9-NEXT:    v_and_b32_e32 v0, v0, v2
; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_bitinsert_b8_var:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_lshlrev_b16 v1.h, v2.l, 15
; GFX12-TRUE16-NEXT:    v_and_b16 v0.h, v1.l, 15
; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT:    v_xor_b16 v1.l, v1.h, -1
; GFX12-TRUE16-NEXT:    v_lshlrev_b16 v0.h, v2.l, v0.h
; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, v1.l
; GFX12-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_bitinsert_b8_var:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_lshlrev_b16 v3, v2, 15
; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 15, v1
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT:    v_xor_b32_e32 v3, -1, v3
; GFX12-FAKE16-NEXT:    v_lshlrev_b16 v1, v2, v1
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v3
; GFX12-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b8 %base, i4 %val, i32 %off
  ret b8 %result
}

define b8 @test_bitinsert_b8_const(b8 %base, i4 %val) {
; GFX9-LABEL: test_bitinsert_b8_const:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_and_b32_e32 v1, 15, v1
; GFX9-NEXT:    v_and_b32_e32 v0, 0xffffff87, v0
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 3, v1
; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_bitinsert_b8_const:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_and_b16 v0.h, v1.l, 15
; GFX12-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, 0xff87
; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 3, v0.h
; GFX12-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_bitinsert_b8_const:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 15, v1
; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffffff87, v0
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT:    v_lshlrev_b16 v1, 3, v1
; GFX12-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b8 %base, i4 %val, i32 3
  ret b8 %result
}

define b21 @test_bitinsert_b21_var(b21 %base, i6 %val, i32 %off) {
; GFX9-LABEL: test_bitinsert_b21_var:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_lshlrev_b32_e64 v3, v2, 63
; GFX9-NEXT:    v_and_b32_e32 v1, 63, v1
; GFX9-NEXT:    v_xor_b32_e32 v3, 0x1fffff, v3
; GFX9-NEXT:    v_lshlrev_b32_e32 v1, v2, v1
; GFX9-NEXT:    v_and_or_b32 v0, v0, v3, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_b21_var:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_lshlrev_b32_e64 v3, v2, 63
; GFX12-NEXT:    v_and_b32_e32 v1, 63, v1
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT:    v_xor_b32_e32 v3, 0x1fffff, v3
; GFX12-NEXT:    v_lshlrev_b32_e32 v1, v2, v1
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT:    v_and_or_b32 v0, v0, v3, v1
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b21 %base, i6 %val, i32 %off
  ret b21 %result
}

define b21 @test_bitinsert_b21_const(b21 %base, i6 %val) {
; GFX9-LABEL: test_bitinsert_b21_const:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_and_b32_e32 v1, 63, v1
; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 14, v1
; GFX9-NEXT:    s_mov_b32 s4, 0x103fff
; GFX9-NEXT:    v_and_or_b32 v0, v0, s4, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_b21_const:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_and_b32_e32 v1, 63, v1
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT:    v_lshlrev_b32_e32 v1, 14, v1
; GFX12-NEXT:    v_and_or_b32 v0, v0, 0x103fff, v1
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b21 %base, i6 %val, i32 14
  ret b21 %result
}

define b123 @test_bitinsert_b123_var(b123 %base, i32 %val, i32 %off) {
; GFX9-LABEL: test_bitinsert_b123_var:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v6, v5
; GFX9-NEXT:    v_sub_u32_e32 v11, 64, v6
; GFX9-NEXT:    s_mov_b64 s[6:7], 0xffffffff
; GFX9-NEXT:    v_subrev_u32_e32 v12, 64, v6
; GFX9-NEXT:    v_lshrrev_b64 v[7:8], v11, s[6:7]
; GFX9-NEXT:    v_lshlrev_b64 v[9:10], v12, s[6:7]
; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v6
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v10, v8, vcc
; GFX9-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v6
; GFX9-NEXT:    v_cndmask_b32_e64 v5, v5, 0, s[4:5]
; GFX9-NEXT:    v_xor_b32_e32 v5, 0x7ffffff, v5
; GFX9-NEXT:    v_cndmask_b32_e32 v7, v9, v7, vcc
; GFX9-NEXT:    v_cndmask_b32_e64 v7, v7, 0, s[4:5]
; GFX9-NEXT:    v_and_b32_e32 v3, v3, v5
; GFX9-NEXT:    v_mov_b32_e32 v5, 0
; GFX9-NEXT:    v_not_b32_e32 v13, v7
; GFX9-NEXT:    v_lshrrev_b64 v[7:8], v11, v[4:5]
; GFX9-NEXT:    v_lshlrev_b64 v[9:10], v12, v[4:5]
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], v6, v[4:5]
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc
; GFX9-NEXT:    v_cndmask_b32_e64 v8, v8, 0, s[4:5]
; GFX9-NEXT:    v_cndmask_b32_e32 v7, v9, v7, vcc
; GFX9-NEXT:    v_cndmask_b32_e64 v9, v7, 0, s[4:5]
; GFX9-NEXT:    v_or_b32_e32 v3, v3, v8
; GFX9-NEXT:    v_lshlrev_b64 v[7:8], v6, s[6:7]
; GFX9-NEXT:    v_and_b32_e32 v2, v2, v13
; GFX9-NEXT:    v_cndmask_b32_e32 v8, 0, v8, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v7, 0, v7, vcc
; GFX9-NEXT:    v_bfi_b32 v1, v8, 0, v1
; GFX9-NEXT:    v_bfi_b32 v0, v7, 0, v0
; GFX9-NEXT:    v_cndmask_b32_e32 v5, 0, v5, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
; GFX9-NEXT:    v_or_b32_e32 v2, v2, v9
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v5
; GFX9-NEXT:    v_or_b32_e32 v0, v0, v4
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_b123_var:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dual_mov_b32 v6, v5 :: v_dual_mov_b32 v5, 0
; GFX12-NEXT:    s_mov_b64 s[2:3], 0xffffffff
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT:    v_sub_nc_u32_e32 v11, 64, v6
; GFX12-NEXT:    v_subrev_nc_u32_e32 v13, 64, v6
; GFX12-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 64, v6
; GFX12-NEXT:    v_cmp_eq_u32_e64 s0, 0, v6
; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT:    v_lshrrev_b64 v[7:8], v11, s[2:3]
; GFX12-NEXT:    v_lshlrev_b64_e64 v[9:10], v13, s[2:3]
; GFX12-NEXT:    v_lshrrev_b64 v[11:12], v11, v[4:5]
; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT:    v_dual_cndmask_b32 v14, v10, v8 :: v_dual_cndmask_b32 v15, v9, v7
; GFX12-NEXT:    v_lshlrev_b64_e32 v[7:8], v13, v[4:5]
; GFX12-NEXT:    v_lshlrev_b64_e64 v[9:10], v6, s[2:3]
; GFX12-NEXT:    v_lshlrev_b64_e32 v[4:5], v6, v[4:5]
; GFX12-NEXT:    s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT:    v_cndmask_b32_e64 v13, v14, 0, s0
; GFX12-NEXT:    v_cndmask_b32_e64 v14, v15, 0, s0
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX12-NEXT:    v_dual_cndmask_b32 v6, v8, v12 :: v_dual_cndmask_b32 v9, 0, v9
; GFX12-NEXT:    v_dual_cndmask_b32 v8, 0, v10 :: v_dual_cndmask_b32 v7, v7, v11
; GFX12-NEXT:    v_xor_b32_e32 v10, 0x7ffffff, v13
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-NEXT:    v_not_b32_e32 v12, v14
; GFX12-NEXT:    v_bfi_b32 v0, v9, 0, v0
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-NEXT:    v_bfi_b32 v1, v8, 0, v1
; GFX12-NEXT:    v_dual_cndmask_b32 v4, 0, v4 :: v_dual_and_b32 v3, v3, v10
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX12-NEXT:    v_dual_cndmask_b32 v5, 0, v5 :: v_dual_and_b32 v2, v2, v12
; GFX12-NEXT:    v_cndmask_b32_e64 v7, v7, 0, s0
; GFX12-NEXT:    v_cndmask_b32_e64 v6, v6, 0, s0
; GFX12-NEXT:    v_or_b32_e32 v0, v0, v4
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-NEXT:    v_or_b32_e32 v1, v1, v5
; GFX12-NEXT:    v_or_b32_e32 v2, v2, v7
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4)
; GFX12-NEXT:    v_or_b32_e32 v3, v3, v6
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b123 %base, i32 %val, i32 %off
  ret b123 %result
}

define b123 @test_bitinsert_b123_crossword(b123 %base, i32 %val) {
; GFX9-LABEL: test_bitinsert_b123_crossword:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_and_b32_e32 v1, 0xfffffff, v1
; GFX9-NEXT:    v_lshlrev_b32_e32 v5, 28, v4
; GFX9-NEXT:    v_lshrrev_b32_e32 v4, 4, v4
; GFX9-NEXT:    s_brev_b32 s4, 15
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v5
; GFX9-NEXT:    v_and_or_b32 v2, v2, s4, v4
; GFX9-NEXT:    v_and_b32_e32 v3, 0x7ffffff, v3
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_b123_crossword:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_and_b32_e32 v1, 0xfffffff, v1
; GFX12-NEXT:    v_lshlrev_b32_e32 v5, 28, v4
; GFX12-NEXT:    v_lshrrev_b32_e32 v4, 4, v4
; GFX12-NEXT:    v_and_b32_e32 v3, 0x7ffffff, v3
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-NEXT:    v_or_b32_e32 v1, v1, v5
; GFX12-NEXT:    v_and_or_b32 v2, v2, 0xf0000000, v4
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b123 %base, i32 %val, i32 60
  ret b123 %result
}


define b123 @test_bitinsert_val_b123_full(b123 %base, b123 %val) {
; GFX9-LABEL: test_bitinsert_val_b123_full:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v3, v7
; GFX9-NEXT:    v_mov_b32_e32 v2, v6
; GFX9-NEXT:    v_mov_b32_e32 v1, v5
; GFX9-NEXT:    v_mov_b32_e32 v0, v4
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_val_b123_full:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dual_mov_b32 v3, v7 :: v_dual_mov_b32 v2, v6
; GFX12-NEXT:    v_dual_mov_b32 v1, v5 :: v_dual_mov_b32 v0, v4
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b123 %base, b123 %val, i32 0
  ret b123 %result
}


define b8 @test_bitinsert_val_b8_full(b8 %base, b8 %val) {
  ; container == value width: full overwrite
; GFX9-LABEL: test_bitinsert_val_b8_full:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v0, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_val_b8_full:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_mov_b32_e32 v0, v1
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b8 %base, b8 %val, i32 0
  ret b8 %result
}

define b32 @test_bitinsert_val_b8_into_b32_var(b32 %base, b8 %val, i32 %off) {
; GFX9-LABEL: test_bitinsert_val_b8_into_b32_var:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_movk_i32 s4, 0xff
; GFX9-NEXT:    v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    v_lshlrev_b32_e64 v2, v2, s4
; GFX9-NEXT:    v_not_b32_e32 v2, v2
; GFX9-NEXT:    v_and_or_b32 v0, v0, v2, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_val_b8_into_b32_var:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_and_b32_e32 v1, 0xff, v1
; GFX12-NEXT:    v_lshlrev_b32_e64 v3, v2, 0xff
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT:    v_lshlrev_b32_e32 v1, v2, v1
; GFX12-NEXT:    v_not_b32_e32 v2, v3
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT:    v_and_or_b32 v0, v0, v2, v1
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b32 %base, b8 %val, i32 %off
  ret b32 %result
}

define b32 @test_bitinsert_val_b8_into_b32_const_mid(b32 %base, b8 %val) {
; GFX9-LABEL: test_bitinsert_val_b8_into_b32_const_mid:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v2, 12
; GFX9-NEXT:    v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT:    s_mov_b32 s4, 0xfff00fff
; GFX9-NEXT:    v_and_or_b32 v0, v0, s4, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_val_b8_into_b32_const_mid:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_and_b32_e32 v1, 0xff, v1
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT:    v_lshlrev_b32_e32 v1, 12, v1
; GFX12-NEXT:    v_and_or_b32 v0, v0, 0xfff00fff, v1
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b32 %base, b8 %val, i32 12
  ret b32 %result
}

define b64 @test_bitinsert_val_b8_into_b64_const_top(b64 %base, b8 %val) {
; GFX9-LABEL: test_bitinsert_val_b8_into_b64_const_top:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 24, v2
; GFX9-NEXT:    v_and_b32_e32 v1, 0xffffff, v1
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v2
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_val_b8_into_b64_const_top:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_lshlrev_b32_e32 v2, 24, v2
; GFX12-NEXT:    v_and_b32_e32 v1, 0xffffff, v1
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT:    v_or_b32_e32 v1, v1, v2
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b64 %base, b8 %val, i32 56
  ret b64 %result
}

define b8 @test_bitinsert_val_b1_into_b8(b8 %base, b1 %val, i32 %off) {
; GFX9-LABEL: test_bitinsert_val_b1_into_b8:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_and_b32_e32 v1, 1, v1
; GFX9-NEXT:    v_lshlrev_b16_e32 v1, v2, v1
; GFX9-NEXT:    v_lshlrev_b16_e64 v2, v2, 1
; GFX9-NEXT:    v_xor_b32_e32 v2, -1, v2
; GFX9-NEXT:    v_and_b32_e32 v0, v0, v2
; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_bitinsert_val_b1_into_b8:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_lshlrev_b16 v1.h, v2.l, 1
; GFX12-TRUE16-NEXT:    v_and_b16 v1.l, v1.l, 1
; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT:    v_xor_b16 v1.h, v1.h, -1
; GFX12-TRUE16-NEXT:    v_lshlrev_b16 v0.h, v2.l, v1.l
; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT:    v_and_b16 v0.l, v0.l, v1.h
; GFX12-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v0.h
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_bitinsert_val_b1_into_b8:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_lshlrev_b16 v3, v2, 1
; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 1, v1
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-FAKE16-NEXT:    v_xor_b32_e32 v3, -1, v3
; GFX12-FAKE16-NEXT:    v_lshlrev_b16 v1, v2, v1
; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, v0, v3
; GFX12-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b8 %base, b1 %val, i32 %off
  ret b8 %result
}

define b32 @test_bitinsert_val_b1_into_b32_const_top(b32 %base, b1 %val) {
; GFX9-LABEL: test_bitinsert_val_b1_into_b32_const_top:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 31, v1
; GFX9-NEXT:    s_brev_b32 s4, -2
; GFX9-NEXT:    v_and_or_b32 v0, v0, s4, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_val_b1_into_b32_const_top:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_lshlrev_b32_e32 v1, 31, v1
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT:    v_and_or_b32 v0, v0, 0x7fffffff, v1
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b32 %base, b1 %val, i32 31
  ret b32 %result
}

define b21 @test_bitinsert_val_b21_full(b21 %base, b21 %val) {
; GFX9-LABEL: test_bitinsert_val_b21_full:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v0, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_val_b21_full:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_mov_b32_e32 v0, v1
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b21 %base, b21 %val, i32 0
  ret b21 %result
}

define b32 @test_bitinsert_val_b21_into_b32_var(b32 %base, b21 %val, i32 %off) {
; GFX9-LABEL: test_bitinsert_val_b21_into_b32_var:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_mov_b32 s4, 0x1fffff
; GFX9-NEXT:    v_and_b32_e32 v1, 0x1fffff, v1
; GFX9-NEXT:    v_lshlrev_b32_e32 v1, v2, v1
; GFX9-NEXT:    v_lshlrev_b32_e64 v2, v2, s4
; GFX9-NEXT:    v_not_b32_e32 v2, v2
; GFX9-NEXT:    v_and_or_b32 v0, v0, v2, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_val_b21_into_b32_var:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_and_b32_e32 v1, 0x1fffff, v1
; GFX12-NEXT:    v_lshlrev_b32_e64 v3, v2, 0x1fffff
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT:    v_lshlrev_b32_e32 v1, v2, v1
; GFX12-NEXT:    v_not_b32_e32 v2, v3
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT:    v_and_or_b32 v0, v0, v2, v1
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b32 %base, b21 %val, i32 %off
  ret b32 %result
}

define b32 @test_bitinsert_val_b21_into_b32_const_top(b32 %base, b21 %val) {
; GFX9-LABEL: test_bitinsert_val_b21_into_b32_const_top:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 11, v1
; GFX9-NEXT:    s_movk_i32 s4, 0x7ff
; GFX9-NEXT:    v_and_or_b32 v0, v0, s4, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_val_b21_into_b32_const_top:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_lshlrev_b32_e32 v1, 11, v1
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT:    v_and_or_b32 v0, v0, 0x7ff, v1
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b32 %base, b21 %val, i32 11
  ret b32 %result
}

define b64 @test_bitinsert_val_b21_into_b64_var(b64 %base, b21 %val, i32 %off) {
; GFX9-LABEL: test_bitinsert_val_b21_into_b64_var:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_mov_b64 s[4:5], 0x1fffff
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], v3, s[4:5]
; GFX9-NEXT:    v_bfi_b32 v5, v5, 0, v1
; GFX9-NEXT:    v_and_b32_e32 v1, 0x1fffff, v2
; GFX9-NEXT:    v_mov_b32_e32 v2, 0
; GFX9-NEXT:    v_lshlrev_b64 v[2:3], v3, v[1:2]
; GFX9-NEXT:    v_bfi_b32 v0, v4, 0, v0
; GFX9-NEXT:    v_or_b32_e32 v1, v5, v3
; GFX9-NEXT:    v_or_b32_e32 v0, v0, v2
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_val_b21_into_b64_var:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v4, 0x1fffff, v2
; GFX12-NEXT:    v_lshlrev_b64_e64 v[6:7], v3, 0x1fffff
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT:    v_lshlrev_b64_e32 v[2:3], v3, v[4:5]
; GFX12-NEXT:    v_bfi_b32 v0, v6, 0, v0
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT:    v_bfi_b32 v1, v7, 0, v1
; GFX12-NEXT:    v_or_b32_e32 v0, v0, v2
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b64 %base, b21 %val, i32 %off
  ret b64 %result
}

define b128 @test_bitinsert_val_b123_into_b128_var(b128 %base, b123 %val, i32 %off) {
; GFX9-LABEL: test_bitinsert_val_b123_into_b128_var:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_sub_u32_e32 v13, 64, v8
; GFX9-NEXT:    v_and_b32_e32 v7, 0x7ffffff, v7
; GFX9-NEXT:    v_lshrrev_b64 v[9:10], v13, v[4:5]
; GFX9-NEXT:    v_lshlrev_b64 v[11:12], v8, v[6:7]
; GFX9-NEXT:    v_subrev_u32_e32 v14, 64, v8
; GFX9-NEXT:    v_or_b32_e32 v12, v12, v10
; GFX9-NEXT:    v_or_b32_e32 v11, v11, v9
; GFX9-NEXT:    v_lshlrev_b64 v[9:10], v14, v[4:5]
; GFX9-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v8
; GFX9-NEXT:    s_mov_b32 s6, -1
; GFX9-NEXT:    s_mov_b32 s7, 0x7ffffff
; GFX9-NEXT:    v_cndmask_b32_e32 v10, v10, v12, vcc
; GFX9-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v8
; GFX9-NEXT:    v_cndmask_b32_e64 v15, v10, v7, s[4:5]
; GFX9-NEXT:    v_cndmask_b32_e32 v7, v9, v11, vcc
; GFX9-NEXT:    v_lshrrev_b64 v[9:10], v13, -1
; GFX9-NEXT:    v_lshlrev_b64 v[11:12], v8, s[6:7]
; GFX9-NEXT:    v_cndmask_b32_e64 v13, v7, v6, s[4:5]
; GFX9-NEXT:    v_lshlrev_b64 v[6:7], v14, -1
; GFX9-NEXT:    v_or_b32_e32 v10, v12, v10
; GFX9-NEXT:    v_or_b32_e32 v9, v11, v9
; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc
; GFX9-NEXT:    v_mov_b32_e32 v10, 0x7ffffff
; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v9, vcc
; GFX9-NEXT:    v_cndmask_b32_e64 v7, v7, v10, s[4:5]
; GFX9-NEXT:    v_cndmask_b32_e64 v6, v6, -1, s[4:5]
; GFX9-NEXT:    v_bfi_b32 v3, v7, 0, v3
; GFX9-NEXT:    v_bfi_b32 v2, v6, 0, v2
; GFX9-NEXT:    v_lshlrev_b64 v[6:7], v8, -1
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], v8, v[4:5]
; GFX9-NEXT:    v_cndmask_b32_e32 v7, 0, v7, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v6, 0, v6, vcc
; GFX9-NEXT:    v_bfi_b32 v1, v7, 0, v1
; GFX9-NEXT:    v_bfi_b32 v0, v6, 0, v0
; GFX9-NEXT:    v_cndmask_b32_e32 v5, 0, v5, vcc
; GFX9-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
; GFX9-NEXT:    v_or_b32_e32 v3, v3, v15
; GFX9-NEXT:    v_or_b32_e32 v2, v2, v13
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v5
; GFX9-NEXT:    v_or_b32_e32 v0, v0, v4
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_val_b123_into_b128_var:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_subrev_nc_u32_e32 v19, 64, v8
; GFX12-NEXT:    v_sub_nc_u32_e32 v15, 64, v8
; GFX12-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 64, v8
; GFX12-NEXT:    s_mov_b32 s0, -1
; GFX12-NEXT:    s_mov_b32 s1, 0x7ffffff
; GFX12-NEXT:    v_lshlrev_b64_e32 v[13:14], v19, v[4:5]
; GFX12-NEXT:    v_and_b32_e32 v7, 0x7ffffff, v7
; GFX12-NEXT:    v_lshrrev_b64 v[9:10], v15, v[4:5]
; GFX12-NEXT:    v_lshrrev_b64 v[15:16], v15, -1
; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT:    v_lshlrev_b64_e64 v[17:18], v8, s[0:1]
; GFX12-NEXT:    v_cmp_eq_u32_e64 s0, 0, v8
; GFX12-NEXT:    v_lshlrev_b64_e32 v[11:12], v8, v[6:7]
; GFX12-NEXT:    v_lshlrev_b64_e32 v[4:5], v8, v[4:5]
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX12-NEXT:    v_or_b32_e32 v16, v18, v16
; GFX12-NEXT:    v_or_b32_e32 v15, v17, v15
; GFX12-NEXT:    v_or_b32_e32 v10, v12, v10
; GFX12-NEXT:    v_or_b32_e32 v20, v11, v9
; GFX12-NEXT:    v_lshlrev_b64_e64 v[11:12], v8, -1
; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT:    v_dual_cndmask_b32 v4, 0, v4 :: v_dual_cndmask_b32 v5, 0, v5
; GFX12-NEXT:    v_cndmask_b32_e32 v14, v14, v10, vcc_lo
; GFX12-NEXT:    v_lshlrev_b64_e64 v[9:10], v19, -1
; GFX12-NEXT:    v_cndmask_b32_e32 v13, v13, v20, vcc_lo
; GFX12-NEXT:    v_dual_cndmask_b32 v12, 0, v12 :: v_dual_cndmask_b32 v11, 0, v11
; GFX12-NEXT:    s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT:    v_cndmask_b32_e64 v7, v14, v7, s0
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX12-NEXT:    v_dual_cndmask_b32 v10, v10, v16 :: v_dual_cndmask_b32 v9, v9, v15
; GFX12-NEXT:    v_cndmask_b32_e64 v6, v13, v6, s0
; GFX12-NEXT:    v_bfi_b32 v1, v12, 0, v1
; GFX12-NEXT:    v_bfi_b32 v0, v11, 0, v0
; GFX12-NEXT:    v_cndmask_b32_e64 v8, v10, 0x7ffffff, s0
; GFX12-NEXT:    v_cndmask_b32_e64 v9, v9, -1, s0
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-NEXT:    v_or_b32_e32 v1, v1, v5
; GFX12-NEXT:    v_or_b32_e32 v0, v0, v4
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-NEXT:    v_bfi_b32 v3, v8, 0, v3
; GFX12-NEXT:    v_bfi_b32 v2, v9, 0, v2
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT:    v_or_b32_e32 v3, v3, v7
; GFX12-NEXT:    v_or_b32_e32 v2, v2, v6
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b128 %base, b123 %val, i32 %off
  ret b128 %result
}

define b128 @test_bitinsert_val_b123_into_b128_const_top(b128 %base, b123 %val) {
; GFX9-LABEL: test_bitinsert_val_b123_into_b128_const_top:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v2, v0
; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 5, v[4:5]
; GFX9-NEXT:    v_lshrrev_b32_e32 v4, 27, v5
; GFX9-NEXT:    v_and_or_b32 v0, v2, 31, v0
; GFX9-NEXT:    v_lshlrev_b64 v[2:3], 5, v[6:7]
; GFX9-NEXT:    v_or_b32_e32 v2, v2, v4
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_val_b123_into_b128_const_top:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_mov_b32_e32 v8, v0
; GFX12-NEXT:    v_lshlrev_b64_e32 v[0:1], 5, v[4:5]
; GFX12-NEXT:    v_lshlrev_b64_e32 v[2:3], 5, v[6:7]
; GFX12-NEXT:    v_lshrrev_b32_e32 v4, 27, v5
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT:    v_and_or_b32 v0, v8, 31, v0
; GFX12-NEXT:    v_or_b32_e32 v2, v2, v4
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b128 %base, b123 %val, i32 5
  ret b128 %result
}

define b231 @test_bitinsert_val_b123_into_b231_var(b231 %base, b123 %val, i32 %off) {
; GFX9-LABEL: test_bitinsert_val_b123_into_b231_var:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v13, 0x7ffffff
; GFX9-NEXT:    buffer_store_dword v13, off, s[0:3], s32 offset:44
; GFX9-NEXT:    v_mov_b32_e32 v13, -1
; GFX9-NEXT:    buffer_store_dword v13, off, s[0:3], s32 offset:36
; GFX9-NEXT:    buffer_store_dword v13, off, s[0:3], s32 offset:40
; GFX9-NEXT:    buffer_store_dword v13, off, s[0:3], s32 offset:32
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:104
; GFX9-NEXT:    v_mov_b32_e32 v10, 0
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:60
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:52
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:28
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:20
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:12
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:4
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:56
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:48
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:24
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:16
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:8
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:120
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:112
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:88
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:80
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:72
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:64
; GFX9-NEXT:    buffer_store_dword v8, off, s[0:3], s32 offset:96
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:124
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:116
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:92
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:84
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:76
; GFX9-NEXT:    buffer_store_dword v10, off, s[0:3], s32 offset:68
; GFX9-NEXT:    buffer_store_dword v9, off, s[0:3], s32 offset:100
; GFX9-NEXT:    v_and_b32_e32 v8, 0x7ffffff, v11
; GFX9-NEXT:    buffer_store_dword v8, off, s[0:3], s32 offset:108
; GFX9-NEXT:    s_lshr_b32 s5, s32, 6
; GFX9-NEXT:    v_lshrrev_b32_e32 v8, 3, v12
; GFX9-NEXT:    s_add_i32 s4, s5, 32
; GFX9-NEXT:    v_and_b32_e32 v13, 24, v8
; GFX9-NEXT:    v_sub_u32_e32 v17, s4, v13
; GFX9-NEXT:    buffer_load_dword v9, v17, s[0:3], 0 offen offset:28
; GFX9-NEXT:    buffer_load_dword v11, v17, s[0:3], 0 offen offset:20
; GFX9-NEXT:    buffer_load_dword v10, v17, s[0:3], 0 offen offset:16
; GFX9-NEXT:    buffer_load_dword v8, v17, s[0:3], 0 offen offset:24
; GFX9-NEXT:    v_and_b32_e32 v14, 63, v12
; GFX9-NEXT:    s_lshr_b32 s5, s32, 6
; GFX9-NEXT:    v_xor_b32_e32 v23, 63, v14
; GFX9-NEXT:    s_add_i32 s4, s5, 0x60
; GFX9-NEXT:    v_sub_u32_e32 v24, s4, v13
; GFX9-NEXT:    buffer_load_dword v14, v17, s[0:3], 0 offen offset:12
; GFX9-NEXT:    s_waitcnt vmcnt(2)
; GFX9-NEXT:    v_lshrrev_b64 v[15:16], 1, v[10:11]
; GFX9-NEXT:    s_waitcnt vmcnt(1)
; GFX9-NEXT:    v_lshlrev_b64 v[8:9], v12, v[8:9]
; GFX9-NEXT:    v_lshrrev_b64 v[15:16], v23, v[15:16]
; GFX9-NEXT:    v_lshlrev_b64 v[10:11], v12, v[10:11]
; GFX9-NEXT:    v_or_b32_e32 v13, v9, v16
; GFX9-NEXT:    v_or_b32_e32 v19, v8, v15
; GFX9-NEXT:    buffer_load_dword v9, v24, s[0:3], 0 offen offset:28
; GFX9-NEXT:    buffer_load_dword v15, v24, s[0:3], 0 offen offset:16
; GFX9-NEXT:    buffer_load_dword v16, v24, s[0:3], 0 offen offset:20
; GFX9-NEXT:    buffer_load_dword v8, v24, s[0:3], 0 offen offset:24
; GFX9-NEXT:    buffer_load_dword v18, v24, s[0:3], 0 offen offset:12
; GFX9-NEXT:    v_xor_b32_e32 v13, 0x7f, v13
; GFX9-NEXT:    v_not_b32_e32 v19, v19
; GFX9-NEXT:    v_and_b32_e32 v13, v7, v13
; GFX9-NEXT:    v_and_b32_e32 v19, v6, v19
; GFX9-NEXT:    s_waitcnt vmcnt(2)
; GFX9-NEXT:    v_lshrrev_b64 v[6:7], 1, v[15:16]
; GFX9-NEXT:    s_waitcnt vmcnt(1)
; GFX9-NEXT:    v_lshlrev_b64 v[8:9], v12, v[8:9]
; GFX9-NEXT:    v_lshrrev_b64 v[6:7], v23, v[6:7]
; GFX9-NEXT:    v_or3_b32 v7, v9, v7, v13
; GFX9-NEXT:    v_or3_b32 v6, v8, v6, v19
; GFX9-NEXT:    buffer_load_dword v9, v17, s[0:3], 0 offen offset:4
; GFX9-NEXT:    buffer_load_dword v13, v17, s[0:3], 0 offen offset:8
; GFX9-NEXT:    buffer_load_dword v8, v17, s[0:3], 0 offen
; GFX9-NEXT:    s_waitcnt vmcnt(1)
; GFX9-NEXT:    v_lshlrev_b64 v[21:22], v12, v[13:14]
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    v_lshrrev_b64 v[19:20], 1, v[8:9]
; GFX9-NEXT:    v_lshrrev_b64 v[13:14], 1, v[13:14]
; GFX9-NEXT:    v_lshrrev_b64 v[19:20], v23, v[19:20]
; GFX9-NEXT:    v_lshrrev_b64 v[13:14], v23, v[13:14]
; GFX9-NEXT:    v_or_b32_e32 v22, v22, v20
; GFX9-NEXT:    v_or_b32_e32 v21, v21, v19
; GFX9-NEXT:    buffer_load_dword v19, v24, s[0:3], 0 offen
; GFX9-NEXT:    buffer_load_dword v20, v24, s[0:3], 0 offen offset:4
; GFX9-NEXT:    buffer_load_dword v17, v24, s[0:3], 0 offen offset:8
; GFX9-NEXT:    v_bfi_b32 v24, v22, 0, v3
; GFX9-NEXT:    v_bfi_b32 v25, v21, 0, v2
; GFX9-NEXT:    v_or_b32_e32 v14, v11, v14
; GFX9-NEXT:    v_bfi_b32 v5, v14, 0, v5
; GFX9-NEXT:    v_lshlrev_b64 v[8:9], v12, v[8:9]
; GFX9-NEXT:    v_bfi_b32 v1, v9, 0, v1
; GFX9-NEXT:    v_bfi_b32 v0, v8, 0, v0
; GFX9-NEXT:    s_waitcnt vmcnt(1)
; GFX9-NEXT:    v_lshrrev_b64 v[2:3], 1, v[19:20]
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    v_lshlrev_b64 v[21:22], v12, v[17:18]
; GFX9-NEXT:    v_lshrrev_b64 v[2:3], v23, v[2:3]
; GFX9-NEXT:    v_or3_b32 v2, v21, v2, v25
; GFX9-NEXT:    v_or_b32_e32 v21, v10, v13
; GFX9-NEXT:    v_lshrrev_b64 v[10:11], 1, v[17:18]
; GFX9-NEXT:    v_lshlrev_b64 v[13:14], v12, v[15:16]
; GFX9-NEXT:    v_lshrrev_b64 v[10:11], v23, v[10:11]
; GFX9-NEXT:    v_bfi_b32 v4, v21, 0, v4
; GFX9-NEXT:    v_or3_b32 v4, v13, v10, v4
; GFX9-NEXT:    v_lshlrev_b64 v[9:10], v12, v[19:20]
; GFX9-NEXT:    v_or3_b32 v3, v22, v3, v24
; GFX9-NEXT:    v_or3_b32 v5, v14, v11, v5
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v10
; GFX9-NEXT:    v_or_b32_e32 v0, v0, v9
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_val_b123_into_b231_var:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    s_mov_b32 s0, 0
; GFX12-NEXT:    v_dual_mov_b32 v13, -1 :: v_dual_mov_b32 v14, 0x7ffffff
; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT:    s_mov_b32 s1, s0
; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT:    v_dual_mov_b32 v15, s0 :: v_dual_mov_b32 v16, s1
; GFX12-NEXT:    s_add_co_i32 s0, s32, 32
; GFX12-NEXT:    scratch_store_b64 off, v[13:14], s32 offset:40
; GFX12-NEXT:    v_mov_b32_e32 v14, v13
; GFX12-NEXT:    s_clause 0x2
; GFX12-NEXT:    scratch_store_b64 off, v[15:16], s32 offset:56
; GFX12-NEXT:    scratch_store_b64 off, v[15:16], s32 offset:48
; GFX12-NEXT:    scratch_store_b64 off, v[13:14], s32 offset:32
; GFX12-NEXT:    v_lshrrev_b32_e32 v13, 3, v12
; GFX12-NEXT:    s_add_co_i32 s1, s32, 0x60
; GFX12-NEXT:    v_and_b32_e32 v11, 0x7ffffff, v11
; GFX12-NEXT:    s_clause 0x7
; GFX12-NEXT:    scratch_store_b64 off, v[15:16], s32 offset:24
; GFX12-NEXT:    scratch_store_b64 off, v[15:16], s32 offset:16
; GFX12-NEXT:    scratch_store_b64 off, v[15:16], s32 offset:8
; GFX12-NEXT:    scratch_store_b64 off, v[15:16], s32
; GFX12-NEXT:    scratch_store_b64 off, v[15:16], s32 offset:88
; GFX12-NEXT:    scratch_store_b64 off, v[15:16], s32 offset:80
; GFX12-NEXT:    scratch_store_b64 off, v[15:16], s32 offset:72
; GFX12-NEXT:    scratch_store_b64 off, v[15:16], s32 offset:64
; GFX12-NEXT:    v_and_b32_e32 v13, 24, v13
; GFX12-NEXT:    s_clause 0x3
; GFX12-NEXT:    scratch_store_b64 off, v[8:9], s32 offset:96
; GFX12-NEXT:    scratch_store_b64 off, v[15:16], s32 offset:120
; GFX12-NEXT:    scratch_store_b64 off, v[15:16], s32 offset:112
; GFX12-NEXT:    scratch_store_b64 off, v[10:11], s32 offset:104
; GFX12-NEXT:    v_and_b32_e32 v25, 63, v12
; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT:    v_sub_nc_u32_e32 v19, s0, v13
; GFX12-NEXT:    v_sub_nc_u32_e32 v23, s1, v13
; GFX12-NEXT:    s_clause 0x1
; GFX12-NEXT:    scratch_load_b64 v[8:9], v19, off offset:24
; GFX12-NEXT:    scratch_load_b64 v[10:11], v19, off offset:16
; GFX12-NEXT:    s_clause 0x1
; GFX12-NEXT:    scratch_load_b64 v[13:14], v23, off offset:24
; GFX12-NEXT:    scratch_load_b64 v[15:16], v23, off offset:16
; GFX12-NEXT:    s_clause 0x1
; GFX12-NEXT:    scratch_load_b64 v[17:18], v19, off offset:8
; GFX12-NEXT:    scratch_load_b64 v[19:20], v19, off
; GFX12-NEXT:    s_clause 0x1
; GFX12-NEXT:    scratch_load_b64 v[21:22], v23, off offset:8
; GFX12-NEXT:    scratch_load_b64 v[23:24], v23, off
; GFX12-NEXT:    v_xor_b32_e32 v37, 63, v25
; GFX12-NEXT:    s_wait_loadcnt 0x7
; GFX12-NEXT:    v_lshlrev_b64_e32 v[8:9], v12, v[8:9]
; GFX12-NEXT:    s_wait_loadcnt 0x6
; GFX12-NEXT:    v_lshrrev_b64 v[25:26], 1, v[10:11]
; GFX12-NEXT:    v_lshlrev_b64_e32 v[10:11], v12, v[10:11]
; GFX12-NEXT:    s_wait_loadcnt 0x4
; GFX12-NEXT:    v_lshrrev_b64 v[27:28], 1, v[15:16]
; GFX12-NEXT:    s_wait_loadcnt 0x3
; GFX12-NEXT:    v_lshlrev_b64_e32 v[29:30], v12, v[17:18]
; GFX12-NEXT:    s_wait_loadcnt 0x2
; GFX12-NEXT:    v_lshrrev_b64 v[31:32], 1, v[19:20]
; GFX12-NEXT:    v_lshrrev_b64 v[17:18], 1, v[17:18]
; GFX12-NEXT:    v_lshlrev_b64_e32 v[19:20], v12, v[19:20]
; GFX12-NEXT:    v_lshrrev_b64 v[25:26], v37, v[25:26]
; GFX12-NEXT:    s_wait_loadcnt 0x0
; GFX12-NEXT:    v_lshrrev_b64 v[35:36], 1, v[23:24]
; GFX12-NEXT:    v_lshlrev_b64_e32 v[23:24], v12, v[23:24]
; GFX12-NEXT:    v_lshrrev_b64 v[31:32], v37, v[31:32]
; GFX12-NEXT:    v_lshrrev_b64 v[17:18], v37, v[17:18]
; GFX12-NEXT:    v_bfi_b32 v0, v19, 0, v0
; GFX12-NEXT:    v_or_b32_e32 v9, v9, v26
; GFX12-NEXT:    v_or_b32_e32 v8, v8, v25
; GFX12-NEXT:    v_lshlrev_b64_e32 v[33:34], v12, v[21:22]
; GFX12-NEXT:    v_lshrrev_b64 v[21:22], 1, v[21:22]
; GFX12-NEXT:    v_lshlrev_b64_e32 v[13:14], v12, v[13:14]
; GFX12-NEXT:    v_lshlrev_b64_e32 v[15:16], v12, v[15:16]
; GFX12-NEXT:    v_or_b32_e32 v0, v0, v23
; GFX12-NEXT:    v_or_b32_e32 v12, v30, v32
; GFX12-NEXT:    v_or_b32_e32 v23, v29, v31
; GFX12-NEXT:    v_or_b32_e32 v11, v11, v18
; GFX12-NEXT:    v_or_b32_e32 v10, v10, v17
; GFX12-NEXT:    v_xor_b32_e32 v9, 0x7f, v9
; GFX12-NEXT:    v_not_b32_e32 v8, v8
; GFX12-NEXT:    v_lshrrev_b64 v[27:28], v37, v[27:28]
; GFX12-NEXT:    v_bfi_b32 v1, v20, 0, v1
; GFX12-NEXT:    v_lshrrev_b64 v[19:20], v37, v[35:36]
; GFX12-NEXT:    v_lshrrev_b64 v[21:22], v37, v[21:22]
; GFX12-NEXT:    v_bfi_b32 v3, v12, 0, v3
; GFX12-NEXT:    v_bfi_b32 v2, v23, 0, v2
; GFX12-NEXT:    v_bfi_b32 v5, v11, 0, v5
; GFX12-NEXT:    v_bfi_b32 v4, v10, 0, v4
; GFX12-NEXT:    v_and_b32_e32 v7, v7, v9
; GFX12-NEXT:    v_and_b32_e32 v6, v6, v8
; GFX12-NEXT:    v_or_b32_e32 v1, v1, v24
; GFX12-NEXT:    v_or3_b32 v3, v34, v20, v3
; GFX12-NEXT:    v_or3_b32 v2, v33, v19, v2
; GFX12-NEXT:    v_or3_b32 v5, v16, v22, v5
; GFX12-NEXT:    v_or3_b32 v4, v15, v21, v4
; GFX12-NEXT:    v_or3_b32 v7, v14, v28, v7
; GFX12-NEXT:    v_or3_b32 v6, v13, v27, v6
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b231 %base, b123 %val, i32 %off
  ret b231 %result
}

define b231 @test_bitinsert_val_b123_into_b231_const_wordcross(b231 %base, b123 %val) {
; GFX9-LABEL: test_bitinsert_val_b123_into_b231_const_wordcross:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_and_b32_e32 v1, 0xfffffff, v1
; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 28, v8
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v2
; GFX9-NEXT:    v_lshrrev_b64 v[2:3], 4, v[8:9]
; GFX9-NEXT:    v_and_b32_e32 v11, 0x7ffffff, v11
; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 28, v10
; GFX9-NEXT:    v_lshrrev_b64 v[12:13], 4, v[10:11]
; GFX9-NEXT:    v_or_b32_e32 v3, v2, v3
; GFX9-NEXT:    v_and_b32_e32 v2, 0xff800000, v5
; GFX9-NEXT:    v_or_b32_e32 v5, v2, v13
; GFX9-NEXT:    v_and_b32_e32 v7, 0x7f, v7
; GFX9-NEXT:    v_alignbit_b32 v4, v11, v10, 4
; GFX9-NEXT:    v_alignbit_b32 v2, v9, v8, 4
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_val_b123_into_b231_const_wordcross:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_and_b32_e32 v11, 0x7ffffff, v11
; GFX12-NEXT:    v_and_b32_e32 v12, 0xfffffff, v1
; GFX12-NEXT:    v_lshrrev_b64 v[1:2], 4, v[8:9]
; GFX12-NEXT:    v_lshlrev_b32_e32 v13, 28, v8
; GFX12-NEXT:    v_lshlrev_b32_e32 v14, 28, v10
; GFX12-NEXT:    v_lshrrev_b64 v[3:4], 4, v[10:11]
; GFX12-NEXT:    v_and_b32_e32 v5, 0xff800000, v5
; GFX12-NEXT:    v_and_b32_e32 v7, 0x7f, v7
; GFX12-NEXT:    v_or_b32_e32 v1, v12, v13
; GFX12-NEXT:    v_or_b32_e32 v3, v14, v2
; GFX12-NEXT:    v_alignbit_b32 v2, v9, v8, 4
; GFX12-NEXT:    v_or_b32_e32 v5, v5, v4
; GFX12-NEXT:    v_alignbit_b32 v4, v11, v10, 4
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b231 %base, b123 %val, i32 60
  ret b231 %result
}

; pointer values

define b64 @test_bitinsert_ptr_var(b64 %base, ptr %val, i32 %off) {
; GFX9-LABEL: test_bitinsert_ptr_var:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_lshlrev_b64 v[5:6], v4, -1
; GFX9-NEXT:    v_lshlrev_b64 v[2:3], v4, v[2:3]
; GFX9-NEXT:    v_bfi_b32 v1, v6, 0, v1
; GFX9-NEXT:    v_bfi_b32 v0, v5, 0, v0
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX9-NEXT:    v_or_b32_e32 v0, v0, v2
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_ptr_var:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_lshlrev_b64_e64 v[5:6], v4, -1
; GFX12-NEXT:    v_lshlrev_b64_e32 v[2:3], v4, v[2:3]
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-NEXT:    v_bfi_b32 v0, v5, 0, v0
; GFX12-NEXT:    v_bfi_b32 v1, v6, 0, v1
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT:    v_or_b32_e32 v0, v0, v2
; GFX12-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b64 %base, ptr %val, i32 %off
  ret b64 %result
}

define b128 @test_bitinsert_ptr_const(b128 %base, ptr %val) {
; GFX9-LABEL: test_bitinsert_ptr_const:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v2, v5
; GFX9-NEXT:    v_mov_b32_e32 v1, v4
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_ptr_const:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dual_mov_b32 v2, v5 :: v_dual_mov_b32 v1, v4
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b128 %base, ptr %val, i32 32
  ret b128 %result
}

; pointers in non-default address spaces

define b64 @test_bitinsert_ptr_addrspace1(b64 %base, ptr addrspace(1) %val, i32 %off) {
; GFX9-LABEL: test_bitinsert_ptr_addrspace1:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_lshlrev_b64 v[5:6], v4, -1
; GFX9-NEXT:    v_lshlrev_b64 v[2:3], v4, v[2:3]
; GFX9-NEXT:    v_bfi_b32 v1, v6, 0, v1
; GFX9-NEXT:    v_bfi_b32 v0, v5, 0, v0
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX9-NEXT:    v_or_b32_e32 v0, v0, v2
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_ptr_addrspace1:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_lshlrev_b64_e64 v[5:6], v4, -1
; GFX12-NEXT:    v_lshlrev_b64_e32 v[2:3], v4, v[2:3]
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-NEXT:    v_bfi_b32 v0, v5, 0, v0
; GFX12-NEXT:    v_bfi_b32 v1, v6, 0, v1
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT:    v_or_b32_e32 v0, v0, v2
; GFX12-NEXT:    v_or_b32_e32 v1, v1, v3
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b64 %base, ptr addrspace(1) %val, i32 %off
  ret b64 %result
}

define b128 @test_bitinsert_ptr_addrspace3_const(b128 %base, ptr addrspace(3) %val) {
; GFX9-LABEL: test_bitinsert_ptr_addrspace3_const:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v5, 0
; GFX9-NEXT:    v_lshlrev_b64 v[4:5], 16, v[4:5]
; GFX9-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
; GFX9-NEXT:    v_or_b32_e32 v1, v1, v5
; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_bitinsert_ptr_addrspace3_const:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v0, 0xffff, v0
; GFX12-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT:    v_lshlrev_b64_e32 v[4:5], 16, v[4:5]
; GFX12-NEXT:    v_or_b32_e32 v0, v0, v4
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT:    v_or_b32_e32 v1, v1, v5
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %result = bitinsert b128 %base, ptr addrspace(3) %val, i32 16
  ret b128 %result
}