llvm-gcc-4.2/gcc/config/arm/neon.md

;; APPLE LOCAL file v7 support. Merge from Codesourcery ;; ARM NEON coprocessor Machine Description ;; Copyright (C) 2006 Free Software Foundation, Inc. ;; Written by CodeSourcery. ;; ;; This file is part of GCC. ;; ;; GCC is free software; you can redistribute it and/or modify it ;; under the terms of the GNU General Public License as published by ;; the Free Software Foundation; either version 2, or (at your option) ;; any later version. ;; ;; GCC is distributed in the hope that it will be useful, but ;; WITHOUT ANY WARRANTY; without even the implied warranty of ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ;; General Public License for more details. ;; ;; You should have received a copy of the GNU General Public License ;; along with GCC; see the file COPYING. If not, write to the Free ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA ;; 02110-1301, USA.

;; Constants for unspecs. (define_constants [(UNSPEC_VPADD 65) (UNSPEC_VPSMIN 66) (UNSPEC_VPUMIN 67) (UNSPEC_VPSMAX 68) (UNSPEC_VPUMAX 69) (UNSPEC_ASHIFT_SIGNED 70) (UNSPEC_ASHIFT_UNSIGNED 71) (UNSPEC_VADD 72) (UNSPEC_VADDL 73) (UNSPEC_VADDW 74) (UNSPEC_VHADD 75) (UNSPEC_VQADD 76) (UNSPEC_VADDHN 77) (UNSPEC_VABS 78) (UNSPEC_VQABS 79) (UNSPEC_VGET_LANE 80) (UNSPEC_VSET_LANE 81) (UNSPEC_VDUP_N 82) (UNSPEC_VCOMBINE 83) (UNSPEC_VGET_HIGH 84) (UNSPEC_VGET_LOW 85) (UNSPEC_VMOVN 87) (UNSPEC_VQMOVN 88) (UNSPEC_VQMOVUN 89) (UNSPEC_VMOVL 90) (UNSPEC_VMUL_LANE 91) (UNSPEC_VMLA_LANE 92) (UNSPEC_VMLAL_LANE 93) (UNSPEC_VQDMLAL_LANE 94) (UNSPEC_VMUL_N 95) (UNSPEC_VCVT 96) (UNSPEC_VEXT 97) (UNSPEC_VREV64 98) (UNSPEC_VREV32 99) (UNSPEC_VREV16 100) (UNSPEC_VBSL 101) (UNSPEC_VLD1 102) (UNSPEC_VLD1_LANE 103) (UNSPEC_VLD1_DUP 104) (UNSPEC_VST1 105) (UNSPEC_VST1_LANE 106) (UNSPEC_VSTRUCTDUMMY 107) (UNSPEC_VLD2 108) (UNSPEC_VLD2_LANE 109) (UNSPEC_VLD2_DUP 110) (UNSPEC_VST2 111) (UNSPEC_VST2_LANE 112) (UNSPEC_VLD3 113) (UNSPEC_VLD3A 114) (UNSPEC_VLD3B 115) (UNSPEC_VLD3_LANE 116) (UNSPEC_VLD3_DUP 117) (UNSPEC_VST3 118) (UNSPEC_VST3A 119) (UNSPEC_VST3B 120) (UNSPEC_VST3_LANE 121) (UNSPEC_VLD4 122) (UNSPEC_VLD4A 123) (UNSPEC_VLD4B 124) (UNSPEC_VLD4_LANE 125) (UNSPEC_VLD4_DUP 126) (UNSPEC_VST4 127) (UNSPEC_VST4A 128) (UNSPEC_VST4B 129) (UNSPEC_VST4_LANE 130) (UNSPEC_VTRN1 131) (UNSPEC_VTRN2 132) (UNSPEC_VTBL 133) (UNSPEC_VTBX 134) (UNSPEC_VAND 135) (UNSPEC_VORR 136) (UNSPEC_VEOR 137) (UNSPEC_VBIC 138) (UNSPEC_VORN 139) (UNSPEC_VCVT_N 140) (UNSPEC_VQNEG 142) (UNSPEC_VMVN 143) (UNSPEC_VCLS 144) (UNSPEC_VCLZ 145) (UNSPEC_VCNT 146) (UNSPEC_VRECPE 147) (UNSPEC_VRSQRTE 148) (UNSPEC_VMUL 149) (UNSPEC_VMLA 150) (UNSPEC_VMLAL 151) (UNSPEC_VMLS 152) (UNSPEC_VMLSL 153) (UNSPEC_VQDMULH 154) (UNSPEC_VQDMLAL 155) (UNSPEC_VQDMLSL 156) (UNSPEC_VMULL 157) (UNSPEC_VQDMULL 158) (UNSPEC_VMLS_LANE 159) (UNSPEC_VMLSL_LANE 160) (UNSPEC_VQDMLSL_LANE 161) (UNSPEC_VDUP_LANE 162) (UNSPEC_VZIP1 163) (UNSPEC_VZIP2 164) (UNSPEC_VUZP1 165) (UNSPEC_VUZP2 166) (UNSPEC_VSRI 167) (UNSPEC_VSLI 168) (UNSPEC_VSRA_N 169) (UNSPEC_VSHL_N 170) (UNSPEC_VQSHL_N 171) (UNSPEC_VQSHLU_N 172) (UNSPEC_VSHLL_N 173) (UNSPEC_VSHR_N 174) (UNSPEC_VSHRN_N 175) (UNSPEC_VQSHRN_N 176) (UNSPEC_VQSHRUN_N 177) (UNSPEC_VSUB 178) (UNSPEC_VSUBL 179) (UNSPEC_VSUBW 180) (UNSPEC_VQSUB 181) (UNSPEC_VHSUB 182) (UNSPEC_VSUBHN 183) (UNSPEC_VCEQ 184) (UNSPEC_VCGE 185) (UNSPEC_VCGT 186) (UNSPEC_VCAGE 187) (UNSPEC_VCAGT 188) (UNSPEC_VTST 189) (UNSPEC_VABD 190) (UNSPEC_VABDL 191) (UNSPEC_VABA 192) (UNSPEC_VABAL 193) (UNSPEC_VMAX 194) (UNSPEC_VMIN 195) (UNSPEC_VPADDL 196) (UNSPEC_VPADAL 197) (UNSPEC_VSHL 198) (UNSPEC_VQSHL 199) (UNSPEC_VPMAX 200) (UNSPEC_VPMIN 201) (UNSPEC_VRECPS 202) (UNSPEC_VRSQRTS 203) (UNSPEC_VMULL_LANE 204) (UNSPEC_VQDMULL_LANE 205) (UNSPEC_VQDMULH_LANE 206)])

;; Double-width vector modes. (define_mode_macro VD [V8QI V4HI V2SI V2SF])

;; Double-width vector modes plus 64-bit elements. ;; LLVM LOCAL use v1di instead of di mode (define_mode_macro VDX [V8QI V4HI V2SI V2SF V1DI])

;; Same, without floating-point elements. (define_mode_macro VDI [V8QI V4HI V2SI])

;; Quad-width vector modes. (define_mode_macro VQ [V16QI V8HI V4SI V4SF])

;; Quad-width vector modes plus 64-bit elements. (define_mode_macro VQX [V16QI V8HI V4SI V4SF V2DI])

;; Same, without floating-point elements. (define_mode_macro VQI [V16QI V8HI V4SI])

;; Same, with TImode added, for moves. (define_mode_macro VQXMOV [V16QI V8HI V4SI V4SF V2DI TI])

;; Opaque structure types wider than TImode. (define_mode_macro VSTRUCT [EI OI CI XI])

;; Number of instructions needed to load/store struct elements. FIXME! (define_mode_attr V_slen [(EI “2”) (OI “2”) (CI “3”) (XI “4”)])

;; Opaque structure types used in table lookups (except vtbl1/vtbx1). (define_mode_macro VTAB [TI EI OI])

;; vtbl suffix for above modes. (define_mode_attr VTAB_n [(TI “2”) (EI “3”) (OI “4”)])

;; Widenable modes. (define_mode_macro VW [V8QI V4HI V2SI])

;; Narrowable modes. (define_mode_macro VN [V8HI V4SI V2DI])

;; All supported vector modes. ;; LLVM LOCAL use v1di instead of di mode (define_mode_macro VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DI V1DI])

;; All supported vector modes (except those with 64-bit integer elements). (define_mode_macro VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF])

;; Supported integer vector modes (not 64 bit elements). (define_mode_macro VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI])

;; Supported integer vector modes ;; LLVM LOCAL use v1di instead of di mode (define_mode_macro VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V1DI])

;; Vector modes, including 64-bit integer elements. ;; LLVM LOCAL use v1di instead of di mode (define_mode_macro VDQX [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V1DI V2DI])

;; Vector modes including 64-bit integer elements, but no floats. ;; LLVM LOCAL use v1di instead of di mode (define_mode_macro VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI V1DI V2DI])

;; Vector modes for float->int conversions. (define_mode_macro VCVTF [V2SF V4SF])

;; Vector modes form int->float conversions. (define_mode_macro VCVTI [V2SI V4SI])

;; Vector modes for doubleword multiply-accumulate, etc. insns. (define_mode_macro VMD [V4HI V2SI V2SF])

;; Vector modes for quadword multiply-accumulate, etc. insns. (define_mode_macro VMQ [V8HI V4SI V4SF])

;; Above modes combined. (define_mode_macro VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF])

;; As VMD, but integer modes only. (define_mode_macro VMDI [V4HI V2SI])

;; As VMQ, but integer modes only. (define_mode_macro VMQI [V8HI V4SI])

;; Above modes combined. (define_mode_macro VMDQI [V4HI V2SI V8HI V4SI])

;; Modes with 8-bit and 16-bit elements. (define_mode_macro VX [V8QI V4HI V16QI V8HI])

;; Modes with 8-bit elements. (define_mode_macro VE [V8QI V16QI])

;; Modes with 64-bit elements only. ;; LLVM LOCAL use v1di instead of di mode (define_mode_macro V64 [V1DI V2DI])

;; Modes with 32-bit elements only. (define_mode_macro V32 [V2SI V2SF V4SI V4SF])

;; (Opposite) mode to convert to/from for above conversions. (define_mode_attr V_CVTTO [(V2SI “V2SF”) (V2SF “V2SI”) (V4SI “V4SF”) (V4SF “V4SI”)])

;; Define element mode for each vector mode. (define_mode_attr V_elem [(V8QI “QI”) (V16QI “QI”) (V4HI “HI”) (V8HI “HI”) (V2SI “SI”) (V4SI “SI”) (V2SF “SF”) (V4SF “SF”) ;; LLVM LOCAL use v1di instead of di mode (V1DI “DI”) (V2DI “DI”)])

;; Mode of pair of elements for each vector mode, to define transfer ;; size for structure lane/dup loads and stores. (define_mode_attr V_two_elem [(V8QI “HI”) (V16QI “HI”) (V4HI “SI”) (V8HI “SI”) (V2SI “V2SI”) (V4SI “V2SI”) (V2SF “V2SF”) (V4SF “V2SF”) ;; LLVM LOCAL use v1di instead of di mode (V1DI “V2DI”) (V2DI “V2DI”)])

;; Similar, for three elements. ;; ??? Should we define extra modes so that sizes of all three-element ;; accesses can be accurately represented? (define_mode_attr V_three_elem [(V8QI “SI”) (V16QI “SI”) (V4HI “V4HI”) (V8HI “V4HI”) (V2SI “V4SI”) (V4SI “V4SI”) (V2SF “V4SF”) (V4SF “V4SF”) ;; LLVM LOCAL use v1di instead of di mode (V1DI “EI”) (V2DI “EI”)])

;; Similar, for four elements. (define_mode_attr V_four_elem [(V8QI “SI”) (V16QI “SI”) (V4HI “V4HI”) (V8HI “V4HI”) (V2SI “V4SI”) (V4SI “V4SI”) (V2SF “V4SF”) (V4SF “V4SF”) ;; LLVM LOCAL use v1di instead of di mode (V1DI “OI”) (V2DI “OI”)])

;; Register width from element mode (define_mode_attr V_reg [(V8QI “P”) (V16QI “q”) (V4HI “P”) (V8HI “q”) (V2SI “P”) (V4SI “q”) (V2SF “P”) (V4SF “q”) ;; LLVM LOCAL use v1di instead of di mode (V1DI “P”) (V2DI “q”)])

;; Wider modes with the same number of elements. (define_mode_attr V_widen [(V8QI “V8HI”) (V4HI “V4SI”) (V2SI “V2DI”)])

;; Narrower modes with the same number of elements. (define_mode_attr V_narrow [(V8HI “V8QI”) (V4SI “V4HI”) (V2DI “V2SI”)])

;; Modes with half the number of equal-sized elements. (define_mode_attr V_HALF [(V16QI “V8QI”) (V8HI “V4HI”) (V4SI “V2SI”) (V4SF “V2SF”) ;; LLVM LOCAL use v1di instead of di mode (V2DI “V1DI”)])

;; Same, but lower-case. (define_mode_attr V_half [(V16QI “v8qi”) (V8HI “v4hi”) (V4SI “v2si”) (V4SF “v2sf”) ;; LLVM LOCAL use v1di instead of di mode (V2DI “v1di”)])

;; Modes with twice the number of equal-sized elements. (define_mode_attr V_DOUBLE [(V8QI “V16QI”) (V4HI “V8HI”) (V2SI “V4SI”) (V2SF “V4SF”) ;; LLVM LOCAL use v1di instead of di mode (V1DI “V2DI”)])

;; Same, but lower-case. (define_mode_attr V_double [(V8QI “v16qi”) (V4HI “v8hi”) (V2SI “v4si”) (V2SF “v4sf”) ;; LLVM LOCAL use v1di instead of di mode (V1DI “v2di”)])

;; Modes with double-width elements. (define_mode_attr V_double_width [(V8QI “V4HI”) (V16QI “V8HI”) (V4HI “V2SI”) (V8HI “V4SI”) ;; LLVM LOCAL use v1di instead of di mode (V2SI “V1DI”) (V4SI “V2DI”)])

;; Mode of result of comparison operations (and bit-select operand 1). (define_mode_attr V_cmp_result [(V8QI “V8QI”) (V16QI “V16QI”) (V4HI “V4HI”) (V8HI “V8HI”) (V2SI “V2SI”) (V4SI “V4SI”) (V2SF “V2SI”) (V4SF “V4SI”) ;; LLVM LOCAL use v1di instead of di mode (V1DI “V1DI”) (V2DI “V2DI”)])

;; Get element type from double-width mode, for operations where we don't care ;; about signedness. (define_mode_attr V_if_elem [(V8QI “i8”) (V16QI “i8”) (V4HI “i16”) (V8HI “i16”) (V2SI “i32”) (V4SI “i32”) ;; LLVM LOCAL use v1di instead of di mode (V1DI “i64”) (V2DI “i64”) (V2SF “f32”) (V4SF “f32”)])

;; Same, but for operations which work on signed values. (define_mode_attr V_s_elem [(V8QI “s8”) (V16QI “s8”) (V4HI “s16”) (V8HI “s16”) (V2SI “s32”) (V4SI “s32”) ;; LLVM LOCAL use v1di instead of di mode (V1DI “s64”) (V2DI “s64”) (V2SF “f32”) (V4SF “f32”)])

;; Same, but for operations which work on unsigned values. (define_mode_attr V_u_elem [(V8QI “u8”) (V16QI “u8”) (V4HI “u16”) (V8HI “u16”) (V2SI “u32”) (V4SI “u32”) ;; LLVM LOCAL use v1di instead of di mode (V1DI “u64”) (V2DI “u64”) (V2SF “f32”) (V4SF “f32”)])

;; Element types for extraction of unsigned scalars. (define_mode_attr V_uf_sclr [(V8QI “u8”) (V16QI “u8”) (V4HI “u16”) (V8HI “u16”) (V2SI “32”) (V4SI “32”) (V2SF “32”) (V4SF “32”)])

(define_mode_attr V_sz_elem [(V8QI “8”) (V16QI “8”) (V4HI “16”) (V8HI “16”) (V2SI “32”) (V4SI “32”) ;; LLVM LOCAL use v1di instead of di mode (V1DI “64”) (V2DI “64”) (V2SF “32”) (V4SF “32”)])

;; Element sizes for duplicating ARM registers to all elements of a vector. (define_mode_attr VD_dup [(V8QI “8”) (V4HI “16”) (V2SI “32”) (V2SF “32”)])

;; Opaque integer types for results of pair-forming intrinsics (vtrn, etc.) (define_mode_attr V_PAIR [(V8QI “TI”) (V16QI “OI”) (V4HI “TI”) (V8HI “OI”) (V2SI “TI”) (V4SI “OI”) (V2SF “TI”) (V4SF “OI”) ;; LLVM LOCAL use v1di instead of di mode (V1DI “TI”) (V2DI “OI”)])

;; Same, but lower-case. (define_mode_attr V_pair [(V8QI “ti”) (V16QI “oi”) (V4HI “ti”) (V8HI “oi”) (V2SI “ti”) (V4SI “oi”) (V2SF “ti”) (V4SF “oi”) ;; LLVM LOCAL use v1di instead of di mode (V1DI “ti”) (V2DI “oi”)])

;; Operations on two halves of a quadword vector. (define_code_macro vqh_ops [plus smin smax umin umax])

;; Same, without unsigned variants (for use with *SFmode pattern). (define_code_macro vqhs_ops [plus smin smax])

;; Assembler mnemonics for above codes. (define_code_attr VQH_mnem [(plus “vadd”) (smin “vmin”) (smax “vmax”) (umin “vmin”) (umax “vmax”)])

;; Signs of above, where relevant. (define_code_attr VQH_sign [(plus “i”) (smin “s”) (smax “s”) (umin “u”) (umax “u”)])

;; Extra suffix on some 64-bit insn names (to avoid collision with standard ;; names which we don't want to define). (define_mode_attr V_suf64 [(V8QI "") (V16QI "") (V4HI "") (V8HI "") (V2SI "") (V4SI "") (V2SF "") (V4SF "") ;; LLVM LOCAL use v1di instead of di mode (V1DI "") (V2DI "")])

;; Scalars to be presented to scalar multiplication instructions ;; must satisfy the following constraints. ;; 1. If the mode specifies 16-bit elements, the scalar must be in D0-D7. ;; 2. If the mode specifies 32-bit elements, the scalar must be in D0-D15. ;; This mode attribute is used to obtain the correct register constraints. (define_mode_attr scalar_mul_constraint [(V4HI “x”) (V2SI “t”) (V2SF “t”) (V8HI “x”) (V4SI “t”) (V4SF “t”)])

;; Attribute used to permit string comparisons against <VQH_mnem> in ;; neon_type attribute definitions. (define_attr “vqh_mnem” “vadd,vmin,vmax” (const_string “vadd”))

;; Classification of NEON instructions for scheduling purposes. ;; Do not set this attribute and the “type” attribute together in ;; any one instruction pattern. (define_attr “neon_type” “neon_int_1,
neon_int_2,
neon_int_3,
neon_int_4,
neon_int_5,
neon_vqneg_vqabs,
neon_vmov,
neon_vaba,
neon_vsma,
neon_vaba_qqq,
neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,
neon_mul_qqq_8_16_32_ddd_32,
neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,
neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,
neon_mla_qqq_8_16,
neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,
neon_mla_qqq_32_qqd_32_scalar,
neon_mul_ddd_16_scalar_32_16_long_scalar,
neon_mul_qqd_32_scalar,
neon_mla_ddd_16_scalar_qdd_32_16_long_scalar,
neon_shift_1,
neon_shift_2,
neon_shift_3,
neon_vshl_ddd,
neon_vqshl_vrshl_vqrshl_qqq,
neon_vsra_vrsra,
neon_fp_vadd_ddd_vabs_dd,
neon_fp_vadd_qqq_vabs_qq,
neon_fp_vsum,
neon_fp_vmul_ddd,
neon_fp_vmul_qqd,
neon_fp_vmla_ddd,
neon_fp_vmla_qqq,
neon_fp_vmla_ddd_scalar,
neon_fp_vmla_qqq_scalar,
neon_fp_vrecps_vrsqrts_ddd,
neon_fp_vrecps_vrsqrts_qqq,
neon_bp_simple,
neon_bp_2cycle,
neon_bp_3cycle,
neon_ldr,
neon_str,
neon_vld1_1_2_regs,
neon_vld1_3_4_regs,
neon_vld2_2_regs_vld1_vld2_all_lanes,
neon_vld2_4_regs,
neon_vld3_vld4,
neon_vst1_1_2_regs_vst2_2_regs,
neon_vst1_3_4_regs,
neon_vst2_4_regs_vst3_vst4,
neon_vst3_vst4,
neon_vld1_vld2_lane,
neon_vld3_vld4_lane,
neon_vst1_vst2_lane,
neon_vst3_vst4_lane,
neon_vld3_vld4_all_lanes,
neon_mcr,
neon_mcr_2_mcrr,
neon_mrc,
neon_mrrc,
neon_ldm_2,
neon_stm_2,
none” (const_string “none”))

;; Predicates used for setting the above attribute.

(define_mode_attr Is_float_mode [(V8QI “false”) (V16QI “false”) (V4HI “false”) (V8HI “false”) (V2SI “false”) (V4SI “false”) (V2SF “true”) (V4SF “true”) ;; LLVM LOCAL use v1di instead of di mode (V1DI “false”) (V2DI “false”)])

(define_mode_attr Scalar_mul_8_16 [(V8QI “true”) (V16QI “true”) (V4HI “true”) (V8HI “true”) (V2SI “false”) (V4SI “false”) (V2SF “false”) (V4SF “false”) ;; LLVM LOCAL use v1di instead of di mode (V1DI “false”) (V2DI “false”)])

(define_mode_attr Is_d_reg [(V8QI “true”) (V16QI “false”) (V4HI “true”) (V8HI “false”) (V2SI “true”) (V4SI “false”) (V2SF “true”) (V4SF “false”) ;; LLVM LOCAL use v1di instead of di mode (V1DI “true”) (V2DI “false”)])

(define_mode_attr V_mode_nunits [(V8QI “8”) (V16QI “16”) (V4HI “4”) (V8HI “8”) (V2SI “2”) (V4SI “4”) (V2SF “2”) (V4SF “4”) ;; LLVM LOCAL use v1di instead of di mode (V1DI “1”) (V2DI “2”)])

;; FIXME: Attributes are probably borked. (define_insn “*neon_mov” [(set (match_operand:VD 0 “nonimmediate_operand” “=w,Uv,w, w, ?r,?w,?r,?r, ?Us”) (match_operand:VD 1 “general_operand” " w,w, Dn,Uvi, w, r, r, Usi,r"))] “TARGET_NEON” { if (which_alternative == 2) { int width, is_valid; static char templ[40];

  is_valid = neon_immediate_valid_for_move (operands[1], <MODE>mode,
    &operands[1], &width);

  gcc_assert (is_valid != 0);

  if (width == 0)
    return "vmov.f32\t%P0, %1  @ <mode>";
  else
    sprintf (templ, "vmov.i%d\t%%P0, %%1  @ <mode>", width);

  return templ;
}

/* FIXME: If the memory layout is changed in big-endian mode, output_move_vfp below must be changed to output_move_neon (which will use the element/structure loads/stores), and the constraint changed to ‘Un’ instead of ‘Uv’. */

switch (which_alternative) { case 0: return “vmov\t%P0, %P1 @ ”; case 1: case 3: return output_move_vfp (operands); case 2: gcc_unreachable (); case 4: return “vmov\t%Q0, %R0, %P1 @ ”; case 5: return “vmov\t%P0, %Q1, %R1 @ ”; default: return output_move_double (operands); } } [(set_attr “neon_type” “neon_int_1,,neon_vmov,,neon_mrrc,neon_mcr_2_mcrr,,,*”) (set_attr “type” “,f_stored,,f_loadd,,,alu,load2,store2”) (set_attr “insn” “,,,,,,mov,,”) (set_attr “length” “4,4,4,4,4,4,8,8,8”) (set_attr “pool_range” “,,,1020,,,,1020,*”) (set_attr “neg_pool_range” “,,,1008,,,,1008,*”)])

(define_insn “*neon_mov” [(set (match_operand:VQXMOV 0 “nonimmediate_operand” “=w,Un,w, w, ?r,?w,?r,?r, ?Us”) (match_operand:VQXMOV 1 “general_operand” " w,w, Dn,Uni, w, r, r, Usi, r"))] “TARGET_NEON” { if (which_alternative == 2) { int width, is_valid; static char templ[40];

  is_valid = neon_immediate_valid_for_move (operands[1], <MODE>mode,
    &operands[1], &width);
  
  gcc_assert (is_valid != 0);
  
  if (width == 0)
    return "vmov.f32\t%q0, %1  @ <mode>";
  else
    sprintf (templ, "vmov.i%d\t%%q0, %%1  @ <mode>", width);
  
  return templ;
}

switch (which_alternative) { case 0: return “vmov\t%q0, %q1 @ ”; case 1: case 3: return output_move_neon (operands); case 2: gcc_unreachable (); case 4: return “vmov\t%Q0, %R0, %e1 @ ;vmov\t%J0, %K0, %f1”; case 5: return “vmov\t%e0, %Q1, %R1 @ ;vmov\t%f0, %J1, %K1”; default: return output_move_quad (operands); } } [(set_attr “neon_type” “neon_int_1,neon_stm_2,neon_vmov,neon_ldm_2,
neon_mrrc,neon_mcr_2_mcrr,,,*”) (set_attr “type” “,,,,,,alu,load4,store4”) (set_attr “insn” “,,,,,,mov,,”) (set_attr “length” “4,8,4,8,8,8,16,8,16”) (set_attr “pool_range” “,,,1020,,,,1020,*”) (set_attr “neg_pool_range” “,,,1008,,,,1008,*”)])

(define_expand “movti” [(set (match_operand:TI 0 “nonimmediate_operand” "") (match_operand:TI 1 “general_operand” ""))] “TARGET_NEON” { })

(define_expand “mov” [(set (match_operand:VSTRUCT 0 “nonimmediate_operand” "") (match_operand:VSTRUCT 1 “general_operand” ""))] “TARGET_NEON” { })

;; APPLE LOCAL begin 6160917 (define_expand “reload_in” [(parallel [(match_operand:VDQW 0 “s_register_operand” “=w”) (match_operand:VDQW 1 “neon_reload_mem_operand” “m”) (match_operand:SI 2 “s_register_operand” “=&r”)])] “TARGET_NEON” " { neon_reload_in (operands, mode); DONE; }")

(define_expand “reload_out” [(parallel [(match_operand:VDQW 0 “neon_reload_mem_operand” “=m”) (match_operand:VDQW 1 “s_register_operand” “w”) (match_operand:SI 2 “s_register_operand” “=&r”)])] “TARGET_NEON” " { neon_reload_out (operands, mode); DONE; }") ;; APPLE LOCAL end 6160917

(define_insn “*neon_mov” [(set (match_operand:VSTRUCT 0 “nonimmediate_operand” “=w,Ut,w”) (match_operand:VSTRUCT 1 “general_operand” " w,w, Ut"))] “TARGET_NEON” { switch (which_alternative) { case 0: return “#”; case 1: case 2: return output_move_neon (operands); default: gcc_unreachable (); } } [(set_attr “length” “<V_slen>,<V_slen>,<V_slen>”)])

(define_split [(set (match_operand:EI 0 “s_register_operand” "") (match_operand:EI 1 “s_register_operand” ""))] “TARGET_NEON && reload_completed” [(set (match_dup 0) (match_dup 1)) (set (match_dup 2) (match_dup 3))] { int rdest = REGNO (operands[0]); int rsrc = REGNO (operands[1]); rtx dest[2], src[2];

dest[0] = gen_rtx_REG (TImode, rdest); src[0] = gen_rtx_REG (TImode, rsrc); dest[1] = gen_rtx_REG (DImode, rdest + 4); src[1] = gen_rtx_REG (DImode, rsrc + 4);

neon_disambiguate_copy (operands, dest, src, 2); })

(define_split [(set (match_operand:OI 0 “s_register_operand” "") (match_operand:OI 1 “s_register_operand” ""))] “TARGET_NEON && reload_completed” [(set (match_dup 0) (match_dup 1)) (set (match_dup 2) (match_dup 3))] { int rdest = REGNO (operands[0]); int rsrc = REGNO (operands[1]); rtx dest[2], src[2];

dest[0] = gen_rtx_REG (TImode, rdest); src[0] = gen_rtx_REG (TImode, rsrc); dest[1] = gen_rtx_REG (TImode, rdest + 4); src[1] = gen_rtx_REG (TImode, rsrc + 4);

neon_disambiguate_copy (operands, dest, src, 2); })

(define_split [(set (match_operand:CI 0 “s_register_operand” "") (match_operand:CI 1 “s_register_operand” ""))] “TARGET_NEON && reload_completed” [(set (match_dup 0) (match_dup 1)) (set (match_dup 2) (match_dup 3)) (set (match_dup 4) (match_dup 5))] { int rdest = REGNO (operands[0]); int rsrc = REGNO (operands[1]); rtx dest[3], src[3];

dest[0] = gen_rtx_REG (TImode, rdest); src[0] = gen_rtx_REG (TImode, rsrc); dest[1] = gen_rtx_REG (TImode, rdest + 4); src[1] = gen_rtx_REG (TImode, rsrc + 4); dest[2] = gen_rtx_REG (TImode, rdest + 8); src[2] = gen_rtx_REG (TImode, rsrc + 8);

neon_disambiguate_copy (operands, dest, src, 3); })

(define_split [(set (match_operand:XI 0 “s_register_operand” "") (match_operand:XI 1 “s_register_operand” ""))] “TARGET_NEON && reload_completed” [(set (match_dup 0) (match_dup 1)) (set (match_dup 2) (match_dup 3)) (set (match_dup 4) (match_dup 5)) (set (match_dup 6) (match_dup 7))] { int rdest = REGNO (operands[0]); int rsrc = REGNO (operands[1]); rtx dest[4], src[4];

neon_disambiguate_copy (operands, dest, src, 4); })

; FIXME: Set/extract/init quads.

(define_insn “vec_set” [(set (match_operand:VD 0 “s_register_operand” “+w”) (vec_merge:VD (match_operand:VD 3 “s_register_operand” “0”) (vec_duplicate:VD (match_operand:<V_elem> 1 “s_register_operand” “r”)) (ashift:SI (const_int 1) (match_operand:SI 2 “immediate_operand” “i”))))] “TARGET_NEON” “vmov%?.<V_uf_sclr>\t%P0[%c2], %1” [(set_attr “predicable” “yes”) (set_attr “neon_type” “neon_mcr”)] )

(define_insn “vec_set” [(set (match_operand:VQ 0 “s_register_operand” “+w”) (vec_merge:VQ (match_operand:VQ 3 “s_register_operand” “0”) (vec_duplicate:VQ (match_operand:<V_elem> 1 “s_register_operand” “r”)) (ashift:SI (const_int 1) (match_operand:SI 2 “immediate_operand” “i”))))] “TARGET_NEON” { int half_elts = GET_MODE_NUNITS (mode) / 2; int elt = INTVAL (operands[2]) % half_elts; int hi = (INTVAL (operands[2]) / half_elts) * 2; int regno = REGNO (operands[0]);

operands[0] = gen_rtx_REG (<V_HALF>mode, regno + hi); operands[2] = GEN_INT (elt);

return “vmov%?.<V_uf_sclr>\t%P0[%c2], %1”; } [(set_attr “predicable” “yes”) (set_attr “neon_type” “neon_mcr”)] )

(define_insn “vec_setv2di” [(set (match_operand:V2DI 0 “s_register_operand” “+w”) (vec_merge:V2DI (match_operand:V2DI 3 “s_register_operand” “0”) (vec_duplicate:V2DI (match_operand:DI 1 “s_register_operand” “r”)) (ashift:SI (const_int 1) (match_operand:SI 2 “immediate_operand” “i”))))] “TARGET_NEON” { int regno = REGNO (operands[0]) + INTVAL (operands[2]);

operands[0] = gen_rtx_REG (DImode, regno);

return “vmov%?.64\t%P0, %Q1, %R1”; } [(set_attr “predicable” “yes”) (set_attr “neon_type” “neon_mcr_2_mcrr”)] )

(define_insn “vec_extract” [(set (match_operand:<V_elem> 0 “s_register_operand” “=r”) (vec_select:<V_elem> (match_operand:VD 1 “s_register_operand” “w”) (parallel [(match_operand:SI 2 “immediate_operand” “i”)])))] “TARGET_NEON” “vmov%?.<V_uf_sclr>\t%0, %P1[%c2]” [(set_attr “predicable” “yes”) (set_attr “neon_type” “neon_bp_simple”)] )

(define_insn “vec_extract” [(set (match_operand:<V_elem> 0 “s_register_operand” “=r”) (vec_select:<V_elem> (match_operand:VQ 1 “s_register_operand” “w”) (parallel [(match_operand:SI 2 “immediate_operand” “i”)])))] “TARGET_NEON” { int half_elts = GET_MODE_NUNITS (mode) / 2; int elt = INTVAL (operands[2]) % half_elts; int hi = (INTVAL (operands[2]) / half_elts) * 2; int regno = REGNO (operands[1]);

operands[1] = gen_rtx_REG (<V_HALF>mode, regno + hi); operands[2] = GEN_INT (elt);

return “vmov%?.<V_uf_sclr>\t%0, %P1[%c2]”; } [(set_attr “predicable” “yes”) (set_attr “neon_type” “neon_bp_simple”)] )

(define_insn “vec_extractv2di” [(set (match_operand:DI 0 “s_register_operand” “=r”) (vec_select:DI (match_operand:V2DI 1 “s_register_operand” “w”) (parallel [(match_operand:SI 2 “immediate_operand” “i”)])))] “TARGET_NEON” { int regno = REGNO (operands[1]) + INTVAL (operands[2]);

operands[1] = gen_rtx_REG (DImode, regno);

return “vmov%?.64\t%Q0, %R0, %P1”; } [(set_attr “predicable” “yes”) (set_attr “neon_type” “neon_int_1”)] )

(define_expand “vec_init” [(match_operand:VDQ 0 “s_register_operand” "") (match_operand 1 "" "")] “TARGET_NEON” { neon_expand_vector_init (operands[0], operands[1]); DONE; })

;; Doubleword and quadword arithmetic.