)]}'
{
  "commit": "dae4cea040cd16ba81b1f1c7ca7ab54a8e9270f1",
  "tree": "ee2e09432a8e36fa8aab7cc34b98acaa5724d33f",
  "parents": [
    "cbf867e363d32a094709f0923db115be7359647a"
  ],
  "author": {
    "name": "Simon Dardis",
    "email": "simon.dardis@mips.com",
    "time": "Fri Mar 16 22:28:08 2018 +0000"
  },
  "committer": {
    "name": "Simon Dardis",
    "email": "simon.dardis@mips.com",
    "time": "Fri Mar 16 22:28:08 2018 +0000"
  },
  "message": "Backporting r325647 and r325713:\n------------------------------------------------------------------------\nr325713 | sdardis | 2018-02-21 20:01:43 +0000 (Wed, 21 Feb 2018) | 5 lines\n\n[mips][lld] Address post commit review nit.\n\nAddress @ruiu\u0027s post commit review comment about a value which is intended\nto be a unsigned 32 bit integer as using uint32_t rather than unsigned.\n\n------------------------------------------------------------------------\n------------------------------------------------------------------------\nr325647 | sdardis | 2018-02-20 23:49:17 +0000 (Tue, 20 Feb 2018) | 27 lines\n\n[mips][lld] Spectre variant two mitigation for MIPSR2\n\nThis patch provides migitation for CVE-2017-5715, Spectre variant two,\nwhich affects the P5600 and P6600. It implements the LLD part of\n-z hazardplt. Like the Clang part of this patch, I have opted for that\nspecific option name in case alternative migitation methods are required\nin the future.\n\nThe mitigation strategy suggested by MIPS for these processors is to use\nhazard barrier instructions. \u0027jalr.hb\u0027 and \u0027jr.hb\u0027 are hazard\nbarrier variants of the \u0027jalr\u0027 and \u0027jr\u0027 instructions respectively.\n\nThese instructions impede the execution of instruction stream until\narchitecturally defined hazards (changes to the instruction stream,\nprivileged registers which may affect execution) are cleared. These\ninstructions in MIPS\u0027 designs are not speculated past.\n\nThese instructions are defined by the MIPS32R2 ISA, so this mitigation\nmethod is not compatible with processors which implement an earlier\nrevision of the MIPS ISA.\n\nFor LLD, this changes PLT stubs to use \u0027jalr.hb\u0027 and \u0027jr.hb\u0027.\n\nReviewers: atanasyan, ruiu\n\nDifferential Revision: https://reviews.llvm.org/D43488\n\n------------------------------------------------------------------------\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/lld/branches/release_50@327757 91177308-0d34-0410-b5e6-96231b3b80d8\n",
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}